Hi all,
Gyula has posted this explanation at the OU topic as the probable cause of the effect.
Hi Luc,
Thanks for your explanations in the second video.
Now my understanding on your circuit is that the MOSFET output capacitance (CDS and the 44.6mH toroidal coil forms a parallel resonant circuit at 18.8kHz. How?
See the data sheet for your IRF640:
http://www.irf.com/product-info/datasheets/data/irf640n.pdfSee Fig. 5 in Page 4, and the output capacitance curve, Coss, shows about 1500-1600pF at 1V drain-source voltage (taken at VGS=0V).
And if you calculate the C value from the 18.8kHz resonant frequency using the 44.6mH toroid coil value, you get 1.61nF capacitor value! (I used this online calculator:
http://www.whatcircuits.com/lc-resonance-frequency-calculator/ )
This explains why the distance of the magnets from the core is so precisely needed to adjust: you simply change and fine tune the toroidal inductance for the best value for getting the highest output voltage which can occur at the highest impedance a parallel LC circuit provides. No resonance=no max output. The drastic change in the output capacitance also explains why you find the "effect" works at no higher than 2.8V DC: the capacitance gets reduced under the 1000pF values and the LC circuit impedance becomes lower and lower. You seem to nicely finetune the output circuit for most favorable match of the components that ensures the highest possible output.
The battery surely limits the rising of the capacitor voltage and there must be some charging current also flowing into the battery from the cap.
The phenomena of your needing to place the battery back into the circuit to get the "effect" again (after that the cap was fully discharged) is explained by also the 'wrong' value of the output capacitance at zero drain-source value: it simply much higher than 1.6nF and the battery voltage brings it within range. (Just check your unused IRF640 drain source output capacitance in itself, not connected anywhere but to a C meter if you have one, first short circuit the gate-source pins with a piece of wire to really switch it off because the higher than 1nF gate-source input cap likes to store voltage for a longer time.)
There remains to explain your flat current trace during the ON time of the FET but unfortunately I cannot give a correct explanation yet. One possibility:
I think the mistery "flat current" trace of mainly zero value is not really zero but its average value is much smaller than for instance in the case of the 10 Ohm resistor. Because the FET switched output resistance looks like to be higher than 10 Ohm due to the low duty cycle drive it receives at the gate-source input. I know this does not fully explain it though, will be thinking on it. And others here are kindly invited to share their thoughts.
rgds, Gyula