I was working on the sim in LTSpice when I saw that partzman had already posted it. Good job partzman.
One thing that I believe is a point of interest is the drive voltage for the FET. From the prior waveforms that were posted by EMJ, I believe his drive voltage is too low leading to the FET quickly coming out of saturation and holding the inductor at some fixed level of current when the inductor begins to saturate. This may account for some missing energy.
Partzman, you have much more drive (15 v) in your sim so won't see the degenerative effect of Rds as the inductor saturates. Your FET will remain saturated.
Actually EMJ specs a deflection transistor, (post 335 NPN horizontal deflection transistor: D1555) not a FET, although his drawing (VIC) shows a FET and if the deflection transistor is driven from his SG it is possible there is not enough base current drive so the transistor comes out of saturation when the core begins to saturate early as seen in his waveforms.
So the question to EMJ: 1) you have spec'd a deflection transistor earlier, but show a FET in your VIC drawing. What device was actually used for the waveforms you posted?
2)Are you driving the transistor or FET from your SG? At what drive voltage?. If it was a deflection transistor that was used for the posted waveforms, it would be helpful to know the drive current capability of the SG and if a base current limiting resistor was used.
All of this is needed for a proper simulation.
---------------------------
"Secrecy, secret societies and secret groups have always been repugnant to a free and open society"......John F Kennedy
|