I always thought this circuit was somewhat "unique", to say the least. Your application of the 4046 is unlike any I have seen before.
The only unique part is the generation of the TL494 clock by the HC4046 with the aid of the op-amps (U3a & U3b).
I have a few questions...
What/where are R1 and C1? Are these the actual inductor and Wima caps or just a proxy for them?
This is the external LC circuit that is probed and driven by this circuit.
Note: when answering this question, I assumed you were asking about the
L1 and C1 ...not about the "R1 and C1".
Was there a particular reason you chose the AD8032's?
Just good op-amps all around. I remember that other jelly-bean op-amps, which I have tried, failed to convert the HC4046 clock into the TL494 clock due to their voltage offsets and slew rate. You are welcome to use other op-amps but if you simulate them make sure to enter full models including all their imperfections.
Are the I and V sense amp gains set to clip the output into a square wave?
More like convert to a square wave using two level voltage hysteresis. The hysteresis provides noise immunity but introduces phase shifts and duty cycle variations (especially when noise is present at the input) - which is the entire problem that is the subject of this thread.
If so, perhaps comparator's would do a better job of producing an edge at the zero crossing of the I and V.
In theory there is no difference between an ideal op-amp and a comparator. The real-world differences are implementation-specific. I used MAX989 comparator in the role of the noisy sine to square converter in the front end and it worked equally well there (not better though). Last but not least, Itsu did not have the MAX989 then and I did not want to complicate his BOM.
Also, with only 15ma of output drive, is the 8032 sufficient to drive R1/C1?
There it is again: the reference to "R1/C1". Are we referring to the same schematic posted
here by Itsu ?
Anyway, the AD8032 in the front end (U2a & U2b) drive only the CMOS inputs of the HC4046 PLL and the 10k hysteresis resistors, so their output current rating is not exceeded.
Why did you not use the 4046 VCO out (with VCO center freq and range selected and reduced via R1/R2)?
Because TL494.pin5 (CT) requires a specific sawtooth analog waveform and the HC4046.pin4 VCO output is a square digital waveform.
Before making further mods to this circuit, or designing a new one, perhaps we should all discuss what phase relationship and between what points in the circuit we are trying to maintain.
The ultimate goal of this circuit is to drive an
arbitrary external LC circuit (L1 & C1) by a push-pull driver, with such frequency that the voltage and current flowing through it are in phase.
However, the goal of this thread is to design a noisysine-to-square converter that does not introduce phase shifts, duty nor cycle variations and is immune to DC components appearing at the input and to being overdriven by excessive input amplitudes.
From the videos, and I may be wrong, it seems that the phase of the inductor current with respect to that of the voltage across the grenade was the particular phase relationship that needed to be maintained.
Grenade and other specific applications of this circuit are off-topic here.
Actually, even the discussion of anything else but the performance of the noisy sine to square converters in the front end is off-topic here, too - I am indulging you though
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Topic: Conventional (non-OU, but related) electronic circuit problem (Read 5653 times)
