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Author Topic: Akula, Ruslan, Stalker, device discussion and replications.  (Read 36607 times)

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just listen to this vid till the end >>>>> https://www.youtube.com/watch?v=JrAf0AD-lWU


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I received my SN74LS56P 50:1 divider chip and was trying to get it to work, but without success.

As can be seen in the attached datasheet, i hooked up a 1250kHz clock signal from my FG (5V DC @ 50 duty cycle) to the CLKA input pin 5.
There was +5V on Vcc pin 2 and ground on pin 4
Qa output (pin 3) was directly connected to the CLKB input pin 1.
But on Qc output pin 8 there was no visible divided signal present (nor on Qb output pin 7 nor on Qa output pin 3).
CLR pin 6 was tight to ground.

The 5V DC input clock signal collapses to 1.5V when attached to the pin 5, so probably this input is too low for the chip to function, but increasing the FG setting to 10V DC makes no difference.

I have 2 chip each behaving similar, so either i have 2 defective chips, or both are counterfeit parts.

I will fiddle around with these chips somewhat longer, but probably have to return to the earlier used 50:1 divider setup.

Itsu
   

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I hooked up a 1250kHz clock signal from my FG (5V DC @ 50 duty cycle) to the CLKA input pin 5.
Verify with a highZ probe and your scope that this signal from the FG really swings from 0V to 5V when not connected to the chip.
Sometimes the FG displays 5V but the amplitude is much higher and damages chips.  This happens because the FG makes its amplitude calculation based on an expectation of a 50Ω load.
   

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Itsu that 50 to 1 chip is an old chip and its not 50/50 EW output and you need 2 clocks for it and other support chips

Whats wrong with the the 4017 will work if you configure it right you just need 2 nothing else.

Do you want me to list the pin out connections  for you ?
« Last Edit: 2023-08-28, 02:11:24 by AlienGrey »


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Verify with a highZ probe and your scope that this signal from the FG really swings from 0V to 5V when not connected to the chip.
Sometimes the FG displays 5V but the amplitude is much higher and damages chips.  This happens because the FG makes its amplitude calculation based on an expectation of a 50Ω load.

I measured the 5V pulse from the FG, and it shows in the screenshot in the blue trace.
When connecting this pulse to the CLKA input (pin 5) via a 1K resistor, it collapses as shown in the yellow trace and this is with or without power (5V) on the chip).

 
So i doubt if the pinout as shown in the datasheet is correct (or the pinout of the chips i have are correct).

Itsu
   

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I measured the 5V pulse from the FG and it shows in the screenshot in the blue trace.
When connecting this pulse to the CLKA input (pin 5) via a 1K resistor, it collapses as shown in the yellow trace and this is with or without power (5V) on the chip).

 
So i doubt if the pinout as shown in the datasheet is correct (or the pinout of the chhips i have are correct).

Itsu
well you have don it! so will a 74HC390  and might be easier to get but 16 pin


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Itsu that 50 to 1 chip is an old chip and its not 50/50 EW output and you need 2 clocks for it and other support chips

Whats wrong with the the 4017 will work if you configure it right you just need 2 nothing else.

Do you want me to list the pin out connections  for you ?

AG,

an LTspice simulation (attached) of your circuit shows it works, but as a 100:1 divider, so something is wrong still, but close.

Itsu
   

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No; some thing wrong on RS line, ist chip must be / by 5 = 300 khz
you must have it / by 10 is wrong.

I have it on the bench now 1.5 mhz in first 4017 13 to 15 and pin 1 = / by 5 = 300khz on pin 10

Then next 4017 / by 10 = 30 khz works on bench here. gives pure sqr wave

Sorry missed pin 1 output  O0
|Sil

note 555 does nothing


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Sorry missed out pin 1 to rest chip at 5 on first 4017.


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OK, thats better, but now i have a 40:1 divider.

Pin 10 is Q4 which is a times 4 divider, so i need times 5 thus Q5 which is pin 1.
Therefor the Reset moves to Q6 pin 5.

Now i have a 50:1 divider using your circuit, 1250kHz in, 25kHz out.

I will build it now.

Itsu
« Last Edit: 2023-08-27, 19:39:14 by Itsu »
   

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Ok, that worked out fine, 50:1 divider by 2x CD4017.

Itsu
   
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   The best conversation you guys have had in years.
   Good to see it...

     NickZ
   

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 :D u2 is set up as  a ring counter, therefor with the reset jumpered to pin 1` as in the circuit diagram 
once started all the outputs below q5 and q5 will divide by 5 as it's counting in a ring. So q6 and above will have no output, but the carry will be a sqr wave as is.

regards

Sil


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Well done @ Itsu and AG for diversifying . It is high time we think outside the box. Just as said before, the originators only gave us clues and not the exact thing. There are many routes to the stream and this is one.  A cascaded decade counter is a sure way to get 50th sub-harmonic frequency as we are seeing now when used in "divide by" arrangements. In order to remove noise, please, connect pin 13 through a pull down resistor of 1meg to the ground and pin 15 through 100k to the ground. This will help from stray switching .

Maxolous
   

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Well done @ Itsu and AG for diversifying . It is high time we think outside the box. Just as said before, the originators only gave us clues and not the exact thing. There are many routes to the stream and this is one.  A cascaded decade counter is a sure way to get 50th sub-harmonic frequency as we are seeing now when used in "divide by" arrangements. In order to remove noise, please, connect pin 13 through a pull down resistor of 1meg to the ground and pin 15 through 100k to the ground. This will help from stray switching .

Maxolous
Hi Max can you scribble on the circuit to show what you mean as both chips behave differently regards Sil


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Back to the SN74LS56 chip which i still did not get to work.

Looking at the data sheet PDF attached earlier, i think it might have something to do with the CLR pin 6.

Presently i have it tied to ground permanently, but it might need to be triggered somehow.
As i can not find any diagram which uses this chip i have no example how it should be used and the data sheet is no help either.

I will try some timed pulses on that CLR pin to see if it activates the outputs.

Itsu 
   

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74LS56 Key Features & Specifications
Supply Voltage 5V
VIH – High-level input Voltage 2V
VIL – Low-level input Voltage 0.7V
Maximum current allowed to draw through each gate output: 8mA
IOL (Max): 16mA
IOH (Max): -1mA
Clock frequency 15MHz
TTL outputs
Low power consumption
74LS56 Pinout
Pin Name   Pin No.   Description
CLK B   1   Clock input B
Vcc   2   Chip Supply Voltage
Qa   3   Chip Output A
GND   4   Ground
CLK A   5   Clock input A
CLR   6   Clear pin
Qb   7   Chip Output b
Qc   8   Chip Output c


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Partly typing over the earlier linked datasheet does not help here.

What i am looking for is the relationship of the CLR signal compared to the other signals.

Itsu
   
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Partly typing over the earlier linked datasheet does not help here.

What i am looking for is the relationship of the CLR signal compared to the other signals.

Itsu

If I understand correctly, you are asking the function of the CLR line from the logic table and it is this- The CLR line is active high.  IOW, when a logic "1" is on the CLR input, all internal circuitry is cleared or reset.  When the CLR is at a logic "0", the clock is able to perform the assigned functions within the chip.

Pm
   

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Partzman, that's what i expected, so i tied the CLR pin to ground, but the chip does not function then (nor with the CLR pin tied to +5V).

Also, when putting several square wave frequencies on this CLR pin it does not seem to function, so i must conclude that this chip is dead (both of them as i have 2!!) or the pinout i use (from the datasheet) is wrong.

I will leave this setup for what it is and use the AG 50:1 divider setup using the 2 CD4017's.

Thanks,   Itsu
   

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Itsu could it be the chips are ex equipment as a lot of the 74 LS have become obsolete there is the 74HC390 they work
but you need to add interface level change circuitry. I can't find a stockist of the 74ls56 or any +by 50 chips.

Sil


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Here is the 74HC390 circuit it is also divide by 50 it's cheap and has 2 off + 5 stages and 2 + by 2 stages
that can be arranged in any format.


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AG,

Thanks for bringing out some facts.
Guys 74HC390 ie a versatile chip.
This is how it works;

1.  Divide by 2.
Signal in pin 1
Signal out in pin 3
Ground 2,4,8,12,14,15

Divide by 4
In 1
Out 13
Gnd 2,4,8,12,14

3. Divide by 5
In 4
Out 7
Gnd 1,2,8,12,14,15

4.  Divide by 10
In 1
Out 7
Tie 3-4
Gnd 2,8,12,14,15

5. Divide by 20
In 1
Out 13
Tie 3-4
Gnd 1,2,8,14,15

6. Divide by 50
Signal in 12
Signal out 7
Tie 1-9, 3-4
Ground 2,8,14,15

7.  Divideby 100
In 12
Out 3
Tie 9-13, 1-2, 4-13
Gnd 2,4,8

Maxolous




   

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It is a double ripple counter. That's two stages of divide by 2 and two of divide by 5.
2,2   5,5
By strapping output into input you can achieve divide by 100

freq/(2*2*5*5) =freq/100

Maxolous
« Last Edit: 2023-09-01, 11:27:18 by Maxolous »
   

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yeah but you need one of the divide by 2 out puts on the output, to get a stable square wave on the output.

Also if you just want divide by 100 a CD4518 can do that or 50 but it's not a square wave. look at it on a
scope it's not stable


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