Working on the Ruslan setup recently and some years ago there was an attempt to create a PLL (Phase Locked Loop) system to keep one of the major modules being the Series LC Resonance module (Inductor coil / Wima cap) in a locked resonance.
Several (Russian) circuits were presented, but most were no true PLL systems and did not work well.
Then verpies designed a PLL system which did work and again was recently referenced to in this Ruslan 2nd attempt thread:
https://www.overunityresearch.com/index.php?topic=3926.msg91004#msg91004
Due to several reasons it was never implemented, one of them being the problem as mentioned in the quote from verpies in that link above being:
QuoteHowever, hysteresis introduces inherent phase shifts of its own, so more effort should be put into improving these i & v comparators in order to eliminate these phase shifts ...but that is nothing difficult or exotic.
If anyone here has a good idea how to improve them easily, please share it.
So in this thread i again will be asking help from anyone able to shed some light on this problem in an attempt to make it better (i.e. no phase shift) and immune to any DC components variations and excessively high amplitudes (overloads).
Below 1st attached is the PLL circuit i am talking about which is a novel combination of the 74H4046 PLL chip and the TL494 PWM controller.
The problem area is the input area (top left) where the voltage and current signals from the Series LC (in phase when in resonance) come in.
The idea is to lock those "in phase when in resonance" V and I signals so it stays in resonance.
Below 2nd small diagram is a quick setup of a small part of that input area to show the problem (hysteresis introduces inherent phase shifts).
I used a FG to mimic the Series LC by inserting a sine wave there.
The screenshot 1 shows that the sine wave (input signal in blue) is not centered symmetrically inside the rectangular wave (yellow) on either side.
That screenshot shows a fairly noiseless input sine wave, but still the phase shift is there, which gets progressively worse when more noise is added to the sine wave see screenshot 2.
See screenshot 3 for a good example.
Finally i made a video showing again the problem here: https://youtu.be/GqDP3NI66cE
Looking for a solution to that problem, so please anyone who has an idea join in to make this circuit even better, but be aware, it must be a universal solution i.e. a frequency independent solution.
Regards Itsu
Quote from: Itsu on 2022.02.04, 15:36:37
Looking for a solution to that problem, so please anyone who has an idea join in to make this circuit even better, but be aware, it must be a universal solution i.e. a frequency independent solution.
Without that condition you could just slap a
fixed frequency Low Pass Filter before the noisy sine to square converter.
If that filter introduces a frequency-dependent phase delay (as most do) then the problem returns.
Itsu,
You could use an Arduino to implement the various PLL functions as is described here using an Arduino Uno-
https://stackoverflow.com/questions/56475382/software-pll-to-generate-3-2-khz-sampling-freq-locked-with-1pps-from-gps-in-ardu
Although I have not done this myself, this is the approach I would use if it were my problem! Also there are much faster boards available, however for 10kHz or so the Uno should suffice to keep the resonant phases under control.
Regards,
Pm
Hi PM,
the PLL itself is no problem, it works fine, only the front-end is prone to the problems (phase shift etc,) mentioned and need improvement.
But thanks for pointing to the arduino for a PLL solution, perhaps the faster ESP32 is a better option here then.
Itsu
Quote from: Itsu on 2022.02.04, 18:20:58
Hi PM,
the PLL itself is no problem, it works fine, only the front-end is prone to the problems (phase shift etc,) mentioned and need improvement.
But thanks for pointing to the arduino for a PLL solution, perhaps the faster ESP32 is a better option here then.
Itsu
OK. What is the reverse capacitance of diodes D3-D6? This could be the cause of the slight output delay of the op amp but I'm sure you have considered that.
Pm
Quote from: partzman on 2022.02.04, 19:14:29
OK. What is the reverse capacitance of diodes D3-D6? This could be the cause of the slight output delay of the op amp but I'm sure you have considered that.
This can be determined experimentally since this circuit is on the breadboard now.
The diodes can be removed altogether and the amplitude of the signal from the FG decreased to 1.2V
pp so the op-amp is not overdriven (which is the purpose of these diodes).
Quote from: verpies on 2022.02.04, 16:52:21
Without that condition you could just slap a fixed frequency Low Pass Filter before the noisy sine to square converter.
Verpies,
I always thought this circuit was somewhat "unique", to say the least. Your application of the 4046 is unlike any I have seen before. I have a few questions...
What/where are R1 and C1? Are these the actual inductor and Wima caps or just a proxy for them?
Was there a particular reason you chose the AD8032's? Are the I and V sense amp gains set to clip the output into a square wave? If so, perhaps comparator's would do a better job of producing an edge at the zero crossing of the I and V. Also, with only 15ma of output drive, is the 8032 sufficient to drive R1/C1?
Why did you not use the 4046 VCO out (with VCO center freq and range selected and reduced via R1/R2)?
Before making further mods to this circuit, or designing a new one, perhaps we should all discuss what phase relationship and between what points in the circuit we are trying to maintain.
From the videos, and I may be wrong, it seems that the phase of the inductor current with respect to that of the voltage across the grenade was the particular phase relationship that needed to be maintained.
Additionally, varying the frequency of the P-P drive to maintain inductor/Wima resonance seems to disregard the effects varying frequency has on grenade tuning.
Just kicking around a few thoughts...
PW
Quote from: partzman on 2022.02.04, 19:14:29
OK. What is the reverse capacitance of diodes D3-D6? This could be the cause of the slight output delay of the op amp but I'm sure you have considered that.
Pm
PM,
the diodes are 1N4148's which have a "diode capacitance" of 4pF according to the data sheet.
I can try verpies his suggestion to remove them, decrease the sine wave to 1.2Vpp and see what happens.
Picowatt,
QuoteWhat/where are R1 and C1? Are these the actual inductor and Wima caps or just a proxy for them?
These are a proxy just to test out the functionality, they are a small toroid with about 100 turns and a small 10nF Wima cap.
Itsu,
The problem seems to be inherent to the AD8032 op amp! See the attached sim which follows your scope traces pretty close. It does not matter if the diodes are connected or not, the delays are still there!
Trying to get a work around or perhaps a different op amp.
Pm
Itsu,
I'm not sure why you are using an asymmetrical power supply but with +-5vdc supplies and a feed forward cap of 1000pf, the phases are near perfect. The 1000pf will most likely affect the network impedance of the actual circuit so this may not work as advertised! Also the diodes are now 1N4148s.
Pm
Edit: I see why you are using the asymmetrical supplies after looking at the 74H4046 data sheet. Perhaps a 1N4148 blocking diode will suffice on the op amp output but may require +_6vdc supplies for the positive level swing for the 4046 input.
Thanks Partzman,
good idea to use the sim, can you attach the spice file please.
I have removed the 4 1N4148's and had to put a 6.8Vpp sine wave to get any square wave output, but then it looks more symmetrical, see screenshot.
But the square wave is more asymmetrical now, adjusting the 100K pot does not change that.
The asymmetrical power supply was / is needed, as i understand it, to create the triangle input into the TL494, but verpies would know.
We might add another +-5vdc supply for this front-end only
Itsu
Hi Itsu,
have you tried something like this ?
Regards,
Vasik
PS As a generic comment - why not use comparator instead of OP Amp ?
Hi Vasik,
yes, that was one of the PLL circuits i used, but turned out to be no real PLL system as i mentioned above, see the conclusion in this video:
https://www.youtube.com/watch?v=zdIf9Pjyuhs
Itsu
Itsu,
The sim file is attached below.
Pm
PM, O0
Quote from: Itsu on 2022.02.04, 20:58:09
Hi Vasik,
yes, that was one of the PLL circuits i used, but turned out to be no real PLL system as i mentioned above, see the conclusion in this video:
https://www.youtube.com/watch?v=zdIf9Pjyuhs
Itsu
Itsu,
this might be irrelevant but I remember Stalker saying that you not supposed to load push pull,
so just a simple "frequency lock" should be enough.
You can check induction heater schematics, they usually have nice voltage/current sensors schematics which you can reuse in your setup.
Regards,
Vasik
Quote from: picowatt on 2022.02.04, 19:42:27
I always thought this circuit was somewhat "unique", to say the least. Your application of the 4046 is unlike any I have seen before.
The only unique part is the generation of the TL494 clock by the HC4046 with the aid of the op-amps (U3a & U3b).
Quote from: picowatt on 2022.02.04, 19:42:27
I have a few questions...
What/where are R1 and C1? Are these the actual inductor and Wima caps or just a proxy for them?
This is the external LC circuit that is probed and driven by this circuit.
Note: when answering this question, I assumed you were asking about the L1 and C1 (https://www.overunityresearch.com/index.php?action=dlattach;topic=4248.0;attach=43272) ...not about the "R1 and C1".
Quote from: picowatt on 2022.02.04, 19:42:27
Was there a particular reason you chose the AD8032's?
Just good op-amps all around. I remember that other jelly-bean op-amps, which I have tried, failed to convert the HC4046 clock into the TL494 clock due to their voltage offsets and slew rate. You are welcome to use other op-amps but if you simulate them make sure to enter full models including all their imperfections.
Quote from: picowatt on 2022.02.04, 19:42:27
Are the I and V sense amp gains set to clip the output into a square wave?
More like convert to a square wave using two level voltage hysteresis. The hysteresis provides noise immunity but introduces phase shifts and duty cycle variations (especially when noise is present at the input) - which is the entire problem that is the subject of this thread.
Quote from: picowatt on 2022.02.04, 19:42:27
If so, perhaps comparator's would do a better job of producing an edge at the zero crossing of the I and V.
In theory there is no difference between an ideal op-amp and a comparator. The real-world differences are implementation-specific. I used MAX989 comparator in the role of the noisy sine to square converter in the front end and it worked equally well there (not better though). Last but not least, Itsu did not have the MAX989 then and I did not want to complicate his BOM.
Quote from: picowatt on 2022.02.04, 19:42:27
Also, with only 15ma of output drive, is the 8032 sufficient to drive R1/C1?
There it is again: the reference to "R1/C1". Are we referring to the same schematic posted
here (https://www.overunityresearch.com/index.php?action=dlattach;topic=4248.0;attach=43272) by Itsu ?
Anyway, the AD8032 in the front end (U2a & U2b) drive only the CMOS inputs of the HC4046 PLL and the 10k hysteresis resistors, so their output current rating is not exceeded.
Quote from: picowatt on 2022.02.04, 19:42:27
Why did you not use the 4046 VCO out (with VCO center freq and range selected and reduced via R1/R2)?
Because TL494.pin5 (CT) requires a specific sawtooth analog waveform and the HC4046.pin4 VCO output is a square digital waveform.
Quote from: picowatt on 2022.02.04, 19:42:27
Before making further mods to this circuit, or designing a new one, perhaps we should all discuss what phase relationship and between what points in the circuit we are trying to maintain.
The ultimate goal of this circuit is to drive an
arbitrary external LC circuit (L1 & C1) by a push-pull driver, with such frequency that the voltage and current flowing through it are in phase.
However, the goal of this thread is to design a noisysine-to-square converter that does not introduce phase shifts, duty nor cycle variations and is immune to DC components appearing at the input and to being overdriven by excessive input amplitudes.
Quote from: picowatt on 2022.02.04, 19:42:27
From the videos, and I may be wrong, it seems that the phase of the inductor current with respect to that of the voltage across the grenade was the particular phase relationship that needed to be maintained.
Grenade and other specific applications of this circuit are off-topic here.
Actually, even the discussion of anything else but the performance of the noisy sine to square converters in the front end is off-topic here, too - I am indulging you though ;).
Quote from: Itsu on 2022.02.04, 20:40:00
The asymmetrical power supply was / is needed, as i understand it, to create the triangle input into the TL494, but verpies would know.
Yes, the asymmetrical power supply was needed to create the sawtooth waveform at the CT input (pin5) of the TL494 chip.
That negative -1.25V supply was just reused in the noisysine-to-square wave converters in the front-end, to accept bipolar feedback signals. A fully symmetrical ± power supply would have been better, but it was just too much hassle at the time.
Automatic zero level adjustment, as depicted in this
TI Application Note (https://www.ti.com/lit/an/snoa989/snoa989.pdf), would work, too, and with AC coupling and ½V
CC virtual ground a unipolar/single supply would be sufficient.
It would be nice for the guys to see a scopeshot of the voltage waveform at TL494.pin5, with respect to ground (even in the TL494 test configuration depicted in its
datasheet on pg.8 (https://www.ti.com/lit/ds/symlink/tl494.pdf)).
Quote from: Vasik041 on 2022.02.04, 20:49:10
As a generic comment - why not use comparator instead of OP Amp ?
I answered this question in my reply to Picowatt
here (https://www.overunityresearch.com/index.php?topic=4248.msg97574#msg97574).
Quote from: partzman on 2022.02.04, 20:30:13
I'm not sure why you are using an asymmetrical power supply
I answered this question in my reply
here (https://www.overunityresearch.com/index.php?topic=4248.msg97575#msg97575).
Quote from: partzman on 2022.02.04, 20:30:13
... but with +-5vdc supplies and a feed forward cap of 1000pf, the phases are near perfect.
What about when some noise is superimposed on the input waveform like this (https://www.overunityresearch.com/index.php?action=dlattach;topic=4248.0;attach=43280) ?
Verpies,
Seems that once I misspoke and referred to "L1" as "R1", I continued on throughout. I did indeed mean to say "L1". Apologies for the confusion...
Quote from: verpies on 2022.02.04, 21:44:56
... the goal of this thread is to design a noisysine-to-square converter that does not introduce phase shifts, duty nor cycle variations and is immune to DC components appearing at the input and to being overdriven by excessive input amplitudes.
Grenade and other specific applications of this circuit are off-topic here.
Actually, even the discussion of anything else but the performance of the noisy sine to square converters in the front end is off-topic here, too - I am indulging you though ;).
Understood...
PW
Itsu,
When you say "frequency independent", is there a range of permissible operation that you can specify? For example, does the desired frequency of operation vary over a limited range (i.e., +/- some small percentage) or are you wanting something with a very wide detection bandwidth?
Is the noise random or are there components that may be synchronous with or harmonically related to the detected signal?
Is the signal to noise ratio depicted in your scope shots representative of the worst case S/N ratio encountered?
PW
Hi Itsu, your circuit drifts because of component values change with component tolerances to temperature, the problem is the frequency would have to track this drift to keep LC in resonance or the other way is to use a xtal frequency stable circuit (digital) to get your 15khz and then use an LC circuit to obtain resonance.
There is always a way to do what your trying to do, other than drawing energy and heating up the device will end in thermal runaway.
Regards Sil
PS there is a more simple way.
Quote from: picowatt on 2022.02.05, 02:52:07
When you say "frequency independent", is there a range of permissible operation that you can specify?
Although I am not him, I think that the front end should not limit the operational frequency range of the remaining circuit.
The 74HC4046 is specified to work up o 18MHz but the TL494 only up to 300kHz (in my experience up to 500kHz with the external clock source).
So 50Hz to 300kHz seems like a reasonable operating frequency range for a universal circuit like that.
I think that eventually the TL494 should be replaced with a faster P-P PWM chip in order for it to be a better match for the much faster HC4046 PLL.
If you have any suggestions about a faster P-P PWM chip, post them in the
New Developments thread (https://www.overunityresearch.com/index.php?topic=3472.msg62527#msg62527) for now.
Quote from: AlienGrey on 2022.02.05, 05:08:40
Hi Itsu, your circuit drifts because of component values change with component tolerances to temperature,
No, no - this circuit does not drift in frequency.
The circuit works well and locks to the LC resonance frequency over a wide range of frequencies.
See
this video (https://youtu.be/wgtnWuuCMDI?t=55) where Itsu purposely saturates the core of the inductor with a permanent magnet in order to change the overall LC resonance frequency. Note that the PLL tracks these frequency changes quite well.
The problem with it is that the front end circuit which conditions the i & v feedback signals is imperfect because it introduces phase shifts. The PLL then locks to these incorrect phase shifted signals quite well.
This thread is not about improving the operation of the PLL (which works very well) but about improving the noisysine-to-square converters in the front end, which do not behave like zero-crossing detectors because of their design with 2 level hysteresis around the zero line - not because of their thermal drift.
The noise comes mainly from low-resistance CSR (including its amplifier, if any) and external noise sources associated with the externally driven LC circuit. The source of this noise is actually off-topic here except for its frequency characteristics as posed in Picowatt's question.
I promise you that once these front-end kinks are ironed out and PCB designed, there will be another thread about the applications of the
entire circuit and its performance.
Quote from: Vasik041 on 2022.02.04, 21:34:53
Itsu,
this might be irrelevant but I remember Stalker saying that you not supposed to load push pull,
so just a simple "frequency lock" should be enough.
You can check induction heater schematics, they usually have nice voltage/current sensors schematics which you can reuse in your setup.
Regards,
Vasik
Thanks Vasik, good to know and perhaps usable in the follow up when we have solved this noise problem.
Itsu
Quote from: picowatt on 2022.02.05, 02:52:07
Itsu,
When you say "frequency independent", is there a range of permissible operation that you can specify? For example, does the desired frequency of operation vary over a limited range (i.e., +/- some small percentage) or are you wanting something with a very wide detection bandwidth?
Is the noise random or are there components that may be synchronous with or harmonically related to the detected signal?
Is the signal to noise ratio depicted in your scope shots representative of the worst case S/N ratio encountered?
PW
PW, see verpies his answer O0
Itsu
Quote from: AlienGrey on 2022.02.05, 05:08:40
Hi Itsu, your circuit drifts because of component values change with component tolerances to temperature, the problem is the frequency would have to track this drift to keep LC in resonance or the other way is to use a xtal frequency stable circuit (digital) to get your 15khz and then use an LC circuit to obtain resonance.
There is always a way to do what your trying to do, other than drawing energy and heating up the device will end in thermal runaway.
Regards Sil
PS there is a more simple way.
I think you are referring to my "not working PLL video" i showed in this post to Vasik: https://www.overunityresearch.com/index.php?topic=4248.msg97569#msg97569 which is not the topic of this discussion.
Itsu
Quote from: verpies on 2022.02.04, 22:02:52
Yes, the asymmetrical power supply was needed to create the sawtooth waveform at the CT input (pin5) of the TL494 chip.
That negative -1.25V supply was just reused in the noisysine-to-square wave converters in the front-end, to accept bipolar feedback signals. A fully symmetrical ± power supply would have been better, but it was just too much hassle at the time.
Automatic zero level adjustment, as depicted in this TI Application Note (https://www.ti.com/lit/an/snoa989/snoa989.pdf), would work, too, and with AC coupling and ½VCC virtual ground a unipolar/single supply would be sufficient.
It would be nice for the guys to see a scopeshot of the voltage waveform at TL494.pin5, with respect to ground (even in the TL494 test configuration depicted in its datasheet on pg.8 (https://www.ti.com/lit/ds/symlink/tl494.pdf)).
Here a screenshot of an other working TL494 running at 15V with its pin 5 signal (green) and one of its output signal (purple) referenced to ground:
Itsu
Quote from: Itsu on 2022.02.05, 11:03:13
Here a screenshot of an other working TL494 running at 15V with its pin 5 signal (green) and one of its output signal (purple) referenced to ground:
I would like to add that the waveforms appearing at pins 6 & 7 of the 74HC4046 chip, have negative excursions below ground, which is the reason why a negative supply is needed for the op-amps U3a and U3b. This info is off-topic.
Can I just run this other idea across you, perhaps the best idea is the Igorek idea where it starts in the kacher coil.
He drives the primary with one frequency and modulates the secondary with another frequency so you have 1/2 wave and 1/4 wave taking off so to speak.
You still need to phase lock it with a 4046 but it becomes much simpler the way he did it over on Vasics thread.
Sil
Quote from: Itsu on 2022.02.05, 10:15:02
PW, see verpies his answer O0
Itsu
Itsu,
Low pass filtering to reduce harmonics and HF noise is of course a first thought. However, requiring the lock-in range to be the full bandwidth of the HC4046, or the TL494, is going to complicate any filter or tracking filter design.
Can the lock-in range instead be made relatively narrow with the center frequency of that range adjusted as required throughout the desired bandwidth?
In other words, are the values of L1 and C1, and their approximate resonant frequency, known beforehand so that the center frequency can be set to that approximation and the lock-in range limited to some narrow bandwidth around that center frequency?
How critical is response time? Can long period averaging of the phase correction be tolerated?
PW
Added:
Is the S/N ratio depicted in your scope shots represent the worst case S/N ratio you have to work with?
Quote from: verpies on 2022.02.05, 07:33:11
If you have any suggestions about a faster P-P PWM chip, post them in the New Developments thread (https://www.overunityresearch.com/index.php?topic=3472.msg62527#msg62527) for now.
Verpies,
Apparently, I do not have permission to view or post in that thread...
PW
Itsu,
If you haven't already found a solution, you might try removing C1 and reducing R1 to a range of 0-50 ohms. Disconnect D1.D2 but leave D3,D4 connected and use the asymmetrical supplies. In simulation, this produces a very small symmetrical phase delay on the rising and falling edges which might be tolerable. This also removes any phase changes with frequency as C1 would create.
Regards,
Pm
Edit: Added sim for clarity.
Quote from: picowatt on 2022.02.05, 15:59:16
Itsu,
Low pass filtering to reduce harmonics and HF noise is of course a first thought. However, requiring the lock-in range to be the full bandwidth of the HC4046, or the TL494, is going to complicate any filter or tracking filter design.
Can the lock-in range instead be made relatively narrow with the center frequency of that range adjusted as required throughout the desired bandwidth?
In other words, are the values of L1 and C1, and their approximate resonant frequency, known beforehand so that the center frequency can be set to that approximation and the lock-in range limited to some narrow bandwidth around that center frequency?
How critical is response time? Can long period averaging of the phase correction be tolerated?
PW
Added:
Is the S/N ratio depicted in your scope shots represent the worst case S/N ratio you have to work with?
PW,
The initial Ruslan design devices were centered around the 17, 27, and 37KHz resonance frequencies and my initial one was 17KHz i think and the last one 24Khz, but i also saw designs with 12Khz, so i would say that the range would be between 10 to 50KHz.
But it can be that verpies has a more universal approach in mind with the limit only set by some components in use like the TL494 with its 300 to 500KHz limit.
I am sure verpies will come back to you on that.
Concerning the response time and S/N ratio, those are still unknowns to me as it was not implemented yet into a real environment (Ruslan).
Itsu
Quote from: partzman on 2022.02.05, 16:17:23
Itsu,
If you haven't already found a solution, you might try removing C1 and reducing R1 to a range of 0-50 ohms. Disconnect D1.D2 but leave D3,D4 connected and use the asymmetrical supplies. In simulation, this produces a very small symmetrical phase delay on the rising and falling edges which might be tolerable. This also removes any phase changes with frequency as C1 would create.
Regards,
Pm
Edit: Added sim for clarity.
PM,
no, no solution found yet, so i will try your suggestions tonight.
Itsu
I have been thinking of the following method to find the time of the zero crossing, which takes advantage of the fact that two neighboring hemicycles which straddle the zero-line most equally and sum closest to zero are the most likely "place" where the zero-crossing occurs.
Take a look at the following scopeshot which depicts the sum of a LF and HF sine waves ( the HF simulates the noise ).
This composite signal crosses the zero-line at multiple times, which makes it hard to find the true time of the LF component's zero-crossing without using an LPF and its frequency dependent phase delay.
I have colored two neighboring hemicycles which straddle the zero-line in red color when they sum close to zero* ...and in blue color when they don't sum close to zero. You must magnify the scopeshot to see these colors well.
Notice that the hemicycles which straddle the zero-line equally and sum to zero (red) are the closest ones to the zero-crossing of the LF sine wave and that condition is independent of the frequency of the superimposed HF signal.
* The area below the zero-line counts as negative and the area above the zero-line counts as positive. When these two areas are equal then they sum to zero.
Quote from: Itsu on 2022.02.05, 18:11:50
PM,
no, no solution found yet, so i will try your suggestions tonight.
Itsu
PM,
the simulation shows identical signals as your simulation (of course) see first picture, but when building this on a breadboard i still have the phase shift, see screenshot below.
Itsu
Quote from: Itsu on 2022.02.05, 20:12:10
...but when building this on a breadboard i still have the phase shift, see screenshot below.
Could you make another scopeshot with a 3
rd trace which shows the voltage at the "+" input of the op-amp ...with the same zero-line as the "-" input ?
Quote from: Itsu on 2022.02.05, 20:12:10
PM,
the simulation shows identical signals as your simulation (of course) see first picture, but when building this on a breadboard i still have the phase shift, see screenshot below.
Itsu
Well that's a disappointment! Maybe Verpies suggestion will shed some light on the problem.
Pm
Quote from: verpies on 2022.02.05, 21:08:09
Could you make another scopeshot with a 3rd trace which shows the voltage at the "+" input of the op-amp ...with the same zero-line as the "-" input ?
The purple trace is on the pin 3 (+) of the opamp:
So the question is why that purple trace goes only -400mV below ground (it should be around -600mV - the full diode voltage drop) while the output of the op-amp is over -1V below ground?
The 10:11 resistive voltage divider should allow over -900mV at that point.
Diodes, diodes, diodes ...and capacitance. Ditching the diodes and adjusting the voltage divider to limit the voltage at the "+" input to be below the amplitude at the "-" input, would require a symmetrical supply rails or virtual ground at ½Vcc.
Quote from: Itsu on 2022.02.05, 20:12:10
PM,
the simulation shows identical signals as your simulation (of course) see first picture, but when building this on a breadboard i still have the phase shift, see screenshot below.
Itsu
Itsu,
My 2 cents...
With asymmetrical supplies, the current thru R2/R3, and hence the forward voltage of D2/D3, will be different for the two output polarities. This produces an asymmetrical threshold voltage at the input. The breadboarded circuit appears to be working as would be expected. It is the simulator that seems to be in error. Perhaps the simulator is modeling the diode forward voltage as a fixed voltage regardless of forward current (which it is not).
Even with symmetrical supplies, I would think the use of D2/D3 would create excessive hysteresis for this app. Are you wanting wanting the large hysteresis to help deal with the noise issue?
As well, diodes are not all that great for setting reference voltages...
PW
Be aware that my bench circuit is modeled after Partzman his latest simulation circuit with the exception that i still have the 100K trimmer for R3.
So R1 is 22 Ohm, R2 is 10K and R3 is unknown as the signals do not change while going to its (R3) range.
Itsu
Ok, the fact that my R3 was not changing the signals made me double check the circuit and it turned out that this R3 was not attached to ground :-[
I probably removed it when changing from a dual opamp (both amps working) setup to a single amp operation we have now.
After fixing this ground issue i now have some signal change when turning this pot.
I have returned the circuit to the original one, so with the 4 diodes and 10K input R1 like below.
The phase shift is still there but much less.
Itsu
This screenshot is from the circuit after Partzman his mod (R1 = 22 Ohm, D1 and D2 removed):
(His D1 / D2 in the sim, my D3 and D4 on the breadboard / diagram).
Seems now very close to the sim signals.
Quote from: Itsu on 2022.02.06, 11:04:44
The phase shift is still there but much less.
Eventually, you can eliminate the phase shift by setting the two hysteresis thresholds differently, but only with non-noisy input signal.
Quote from: Itsu on 2022.02.06, 11:12:24
This screenshot is from the circuit after Partzman his mod (R1 = 22 Ohm, D1 and D2 removed):
(His D1 / D2 in the sim, my D3 and D4 on the breadboard / diagram).
Seems now very close to the sim signals.
Ahh, that's better! O0
Pm
Quote from: Itsu on 2022.02.06, 11:04:44
Ok, the fact that my R3 was not changing the signals made me double check the circuit and it turned out that this R3 was not attached to ground :-[
I probably removed it when changing from a dual opamp (both amps working) setup to a single amp operation we have now.
After fixing this ground issue i now have some signal change when turning this pot.
I have returned the circuit to the original one, so with the 4 diodes and 10K input R1 like below.
The phase shift is still there but much less.
Itsu
Itsu,
You have reduced the error by reducing the hysteresis, but with the different Vfwd's on D5 an D6 due to the assymetrical rails, this error will vary as you vary the amount of hysterisis.
My suggestion would be to operate the comparators on just the 6 volt rail, generate a mid-rail reference (buffered voltage divider) to use for signal ground connections, and AC couple the inputs. Your waveforms will be symmetrical and that symmetry will not change as you adjust hysteresis.
Regarding the noise issue, I would add some analog signal conditioning in front of the comparators. Consider adding an AC coupled variable gain stage and a LP filter in front of the comparators. What order of filter you will need is dependent on the amount and type of noise you are dealing with (a 4th to 8th order filter comes to mind). With a sufficiently slow loop filter at the PLL, truly random noise (i.e., white noise) will average out to a zero phase error. Non-random noise (i.e., spurious or synchronous signals) can be a bit more problematic, but with a LP filter of sufficient order, adjustment of comparator hysteresis, and a slow PLL loop filter, their contribution to phase errors will be reduced significantly.
Using identical analog front ends (i.e., the same gain, filter, and comparator circuits) will null out the phase shifts caused by these stages.
Fixed frequency analog filters will need to be modified for operation at each of the various frequencies you mentioned. If you need truly variable frequency capability, there are some switched capacitor options available to use as tracking filters, but at frequencies greater than 100KHz, these options become limited and more complex. However, I would think variable frequency operation over a large bandwidth would be unnecessary unless you plan to somehow vary L1 or C1 by large amounts during operation. Modifying the passband of fixed filters for each of the desired frequencies of operation would be a simpler solution.
Using diff amps at the front-end would allow detection of I and V with a non-ground referenced L1/C1 (i.e., using a sense coil and a matched pair of voltage dividers for I and V detection).
I would also consider adding an adjustable mono stable between one of the comparator outputs and its PLL input to allow for adjustment of I/V phase.
You mention Ruslan type circuits. However, can you provide more details as to why L1 and C1 are being driven by an opamp in the OP schematic?
PW
Quote from: picowatt on 2022.02.06, 19:20:49
Itsu,
You have reduced the error by reducing the hysteresis, but with the different Vfwd's on D5 an D6 due to the assymetrical rails, this error will vary as you vary the amount of hysterisis.
My suggestion would be to operate the comparators on just the 6 volt rail, generate a mid-rail reference (buffered voltage divider) to use for signal ground connections, and AC couple the inputs. Your waveforms will be symmetrical and that symmetry will not change as you adjust hysteresis.
Regarding the noise issue, I would add some analog signal conditioning in front of the comparators. Consider adding an AC coupled variable gain stage and a LP filter in front of the comparators. What order of filter you will need is dependent on the amount and type of noise you are dealing with (a 4th to 8th order filter comes to mind). With a sufficiently slow loop filter at the PLL, truly random noise (i.e., white noise) will average out to a zero phase error. Non-random noise (i.e., spurious or synchronous signals) can be a bit more problematic, but with a LP filter of sufficient order, adjustment of comparator hysteresis, and a slow PLL loop filter, their contribution to phase errors will be reduced significantly.
Using identical analog front ends (i.e., the same gain, filter, and comparator circuits) will null out the phase shifts caused by these stages.
Fixed frequency analog filters will need to be modified for operation at each of the various frequencies you mentioned. If you need truly variable frequency capability, there are some switched capacitor options available to use as tracking filters, but at frequencies greater than 100KHz, these options become limited and more complex. However, I would think variable frequency operation over a large bandwidth would be unnecessary unless you plan to somehow vary L1 or C1 by large amounts during operation. Modifying the passband of fixed filters for each of the desired frequencies of operation would be a simpler solution.
Using diff amps at the front-end would allow detection of I and V with a non-ground referenced L1/C1 (i.e., using a sense coil and a matched pair of voltage dividers for I and V detection).
I would also consider adding an adjustable mono stable between one of the comparator outputs and its PLL input to allow for adjustment of I/V phase.
You mention Ruslan type circuits. However, can you provide more details as to why L1 and C1 are being driven by an opamp in the OP schematic?
PW
PW,
thanks for these elaborate set of suggestions which sounds to me like a significant overhaul of the front-end part.
I am sure verpies will be commenting on them.
QuoteYou mention Ruslan type circuits. However, can you provide more details as to why L1 and C1 are being driven by an opamp in the OP schematic?
Concerning this question, the objective was to drive the Series LC (inductor / Wima cap) with a PLL system to have a stable frequency.
As the originally used PWM was a TL494, verpies designed a PLL system around this PWM so it can be used in a PLL system.
So we have this PLL locked TL494 to drive the Yoke and thus the Inductor / Grenade in the normal way (TL494 output to MOSFET drivers / MOSFETs to Yoke etc.) with the feedback of the voltage and current phases into the 74H4046 driving this TL494.
To test if this would work (the PLL 4046 / TL494) we tried the diagram as presented in post #1, where we use 1 output of the TL494 (square wave), convert it to sine wave, add some gain to it and feed it back to a series LC under test (C1/L1).
But again, it could be verpies had a more universal concept in mind, so adaptations to a specific "Ruslan type of environment" needs to be straightened out.
Itsu
Quote from: picowatt on 2022.02.06, 19:20:49
My suggestion would be to operate the comparators on just the 6 volt rail, generate a mid-rail reference (buffered voltage divider) to use for signal ground connections, and AC couple the inputs. Your waveforms will be symmetrical and that symmetry will not change as you adjust hysteresis.
I think this is a good idea. Alone, it will not help with the noise, though.
Quote from: picowatt on 2022.02.06, 19:20:49
Regarding the noise issue, I would add some analog signal conditioning in front of the comparators. Consider adding an AC coupled variable gain stage and a LP filter in front of the comparators.
That filter would need to be retuned below specific PLL capture frequencies for each particular application.
Quote from: picowatt on 2022.02.06, 19:20:49
Fixed frequency analog filters will need to be modified for operation at each of the various frequencies you mentioned.
Oh, you just essentially wrote the same thing.
Quote from: picowatt on 2022.02.06, 19:20:49
What order of filter you will need is dependent on the amount and type of noise you are dealing with (a 4th to 8th order filter comes to mind).
What filter topology would you suggest for the
least variability of phase delay vs. frequency (grp dly), in the passband ?
Quote from: picowatt on 2022.02.06, 19:20:49
Using identical analog front ends (i.e., the same gain, filter, and comparator circuits) will null out the phase shifts caused by these stages.
Yes, but only if the noise characteristics on both channels are identical. In Itsu's experience the signal from the CSR is much more noiser than the voltage signal.
Quote from: picowatt on 2022.02.06, 19:20:49
However, I would think variable frequency operation over a large bandwidth would be unnecessary unless you plan to somehow vary L1 or C1 by large amounts during operation.
I agree. The large bandwidth is only for the universality of the circuit in multiple applications.
Quote from: picowatt on 2022.02.06, 19:20:49
Using diff amps at the front-end would allow detection of I and V with a non-ground referenced L1/C1 (i.e., using a sense coil and a matched pair of voltage dividers for I and V detection).
An advanced yet inexpensive idea to minimize the common mode noise ingress at the input. I forgot about it. Thanks for the reminder.
Quote from: picowatt on 2022.02.06, 19:20:49
I would also consider adding an adjustable mono stable between one of the comparator outputs and its PLL input to allow for adjustment of I/V phase.
Wouldn't manipulation of the phase detector in the PLL chip accomplish the same result?
Quote from: picowatt on 2022.02.06, 19:20:49
You mention Ruslan type circuits. However, can you provide more details as to why L1 and C1 are being driven by an opamp in the OP schematic?
I know the answer to this one:
That was just a proof of concept with the op-amp Itsu had on the breadboard. He knows well that the AD8032 is not suitable for driving high power loads. In a real application, such as the one you mentioned, the LC circuit would be driven by power MOSFETs driven by the PWM Controller (the TL494 in the first version of this circuit or a faster one in future versions).
Quote from: Itsu on 2022.02.06, 21:12:01
thanks for these elaborate set of suggestions which sounds to me like a significant overhaul of the front-end part.
Definitely - prepare yourself for it mentally.
Quote from: verpies on 2022.02.06, 21:14:04
What filter topology would you suggest for the least variability of phase delay vs. frequency (grp dly), in the passband ?
I'd consider an 8th order lowpass using a quad opamp with four unity gain Sallen Key filters (depending on the type of noise and the S/N ratio, a lower order filter may suffice). Group delay will indeed be ugly, but if the two filters are well matched, a phase trim somewhere in the system should allow mismatches to be trimmed out. The type of filter selected will depend on the makeup of the noise to be rejected.
The Bessel filter produces a milder slope with regard to group delay versus frequency as the cutoff frequency is approached. However, an 8th order Bessel will only give you about 30dB of rejection at the nearest harmonic. The 8th order Butterworth has a much steeper group delay slope as cutoff is approached, but will provide more like 60dB of rejection of the nearest harmonic.
Because both inputs will see the same frequency, the phase errors should be consistent and, as above, able to be trimmed somewhere else in the system.
The advantage to using analog filters is that they are low noise and relatively easy to implement. The disadvantage is that components will need to be low tolerance with low Tc and in order to change the frequency, components will need to be changed for each desired frequency of operation.
From a hardware standpoint, a much simpler solution is to use a switched cap filter. One that comes to mind is the 10th order lowpass filter LTC1569-7 (they are a bit pricey @$15 each, but if you are willing to wait for shipment from China, I have seen them go for $5 or so). The advantage of using this filter is that they are easily tuned to the desired frequency via an external clock, with no hardware changes required, and are usable up to just over 300KHz. They have a nearly constant group delay at around 18us that only changes to 17us around the cutoff frequency (and with excellent chip to chip matching). They have a very steep rolloff above the cutoff frequency and could, with relative ease, be incorporated as a tracking filter.
They do require a clock (32X) and will need an anti-alias filter on the front-end and a LP at the output to remove residual clock noise. However, because the clock is 32X the cutoff frequency, these can typically be low order RC filters.
Quote
Yes, but only if the noise characteristics on both channels are identical. In Itsu's experience the signal from the CSR is much more noiser than the voltage signal.
Regardless of which filter type is used, I do not believe that the "flavor" or amount of noise will have an influence on the phase error through the two filters. The frequency of interest will be the same for both filters and group delay will be somewhat matched between the filters. As long as low Tc components are used, any phase error difference between the filters should be rather static and able to be trimmed out somewhere in the system.
Regarding Itsu's greater noise at the Isense leg, this is why I suggest a proper low noise amplifier in front of the filters. Not only will this reduce noise, but it will allow Rsense to be reduced to more realistic values.
Quote
An advanced yet inexpensive idea to minimize the common mode noise ingress at the input. I forgot about it. Thanks for the reminder.
I would consider a three opamp IA configuration at the front-end (yes Itsu, even more complexity...). The advantage is the ease with which gain can be adjusted without messing with the CMRR. There are some low cost resistor arrays available with 0.1% matching and low Tc that are great for this application that will allow for excellent CMRR without trimming. Use of low noise opamps and low impedances will also keep noise to a minimum. And, as mentioned in my previous post, broadband random noise (i.e., thermal noise) will average out to zero phase error given sufficiently slow PLL time constants.
QuoteWouldn't manipulation of the phase detector in the PLL chip accomplish the same result?
Yes, I suppose it would, but how would you do that? I don't see how you could actually manipulate the edge sensitive PC2 in the 4046, particularly if not using the VCO as one of the PC inputs. The use of a monostable on one sense leg, as I mentioned, was just a quick thought with regard to nulling out any filter induced phase errors.
Regarding the 4046, does adjusting RV4 (OP schematic) provide some degree of phase trim? I had considered using the VCO output to feed an edge detector with those edges used to reset an integrator to provide the 2X sawtooth for the 494. Doing so would, however, require modifying/adjusting the integrator or current source for wide ranges of frequencies. As I said, your solution was rather unique. Tip of the hat to ya'...
QuoteI know the answer to this one:
That was just a proof of concept with the op-amp Itsu had on the breadboard. He knows well that the AD8032 is not suitable for driving high power loads. In a real application, such as the one you mentioned, the LC circuit would be driven by power MOSFETs driven by the PWM Controller (the TL494 in the first version of this circuit or a faster one in future versions).
Seeing how the Ruslan type threads began to decompose about the time people thought copper was being transmuted to steel based on a YT video, and have pretty much gone silent since, are there active threads on this forum where this continues to be pursued in private or closed to the public threads?
For example, the apparently limited access to the "New Developments" thread you linked to?
Just wondering...
PW
Hi PW,
impressive post, thanks O0
Concerning the Ruslan thread: as far as i know there are no "private or closed to the public threads" on this forum for this item at the moment.
I was hoping for someone to pick it up and continue with another owner / moderator, but that is not the case.
Itsu
Itsu,
Before settling on a front end design, it might be useful to discuss the measurement environment.
In your OP schematic L1/C1 are ground referenced. If I recall, of the many circuits presented, some did have the inductor leg ground referenced, some did not. As your desire is for a somewhat universal method to maintain resonance, will all desired applications have a ground referenced L1/C1?
If L1/C1 are not ground referenced, additional issues will need to be addressed.
PW
PW,
good question, the Stalker device did not have the Inductor / Wima cap series LC ground referenced / connected see 2nd diagram:
https://www.overunityresearch.com/index.php?topic=3926.msg91690#msg91690
and if i remember correctly neither did the ones i had build before because there was always the problem with ground loops to deal with for scoping signals.
But i know i have done some testing with the series LC connected to ground without seeing much difference in the signals and there are diagrams showing it ground connected.
So what are these "additional issues which will need to be addressed" if L1/C1 are not ground referenced? If not very massive then i suggest to incorporate them.
By the way, i have asked Peter to add you that "new developments" thread verpies was referring to.
Itsu
Quote from: Itsu on 2022.02.08, 16:35:30
So what are these "additional issues which will need to be addressed" if L1/C1 are not ground referenced? If not very massive then i suggest to incorporate them.
Itsu,
With L1/C1 ground referenced, I and V sensing should be a rather trivial matter. You'll want a gain stage driving a filter which then drives your comparator.
I'd start with a simple AC coupled gain stage that has a low resistance connected across the input with simple first (or second) order LP filtering for anti-aliasing. For the Isense leg, the input resistor would be a low value CSR, for the Vsense leg, that resistor would be the low value portion of a resistive divider, with the higher resistance leg being connected to the Vsense point. The voltage seen at the inputs will be very low, and ground referenced, so minimal input protection and bandwidth limiting will be required for the input amplifiers. The only component that will require special attention with regard to the operating environment (HV, corona, etc.) would be the resistor used for the high resistance side of the Vsense voltage divider. That resistor can be a high voltage resistor or a string of lower voltage resistors in series to achieve the required holdoff voltage and low capacitance.
Regarding the gain stage, I'd want the value of the input resistors low enough to require some amount of adjustable gain to drive the filters at a level sufficient for good S/N performance from the filter, while avoiding any clipping from either the center frequency or any noise/HF components present at the input. As well, the frequency response of the input amplifier can be tailored to produce a LF roll-off to provide LF rejection of the mains frequency, etc.
For the filter, I'd go with the aforementioned switched cap filter (LTC1569-7). The VCO output from a single 4046 can be used to clock both filters (one filter each for the I and V sense legs). This allows simple DC control of the filter cutoff frequency via a trimpot at the 4046 VCO input (this is a separate 4046 for filter clocking, not the PLL).
The output of the filter should drive a buffered RC low pass for removal of clock feed-through. The buffer output then drives the comparator.
This may sound complicated but its really not. Hardware wise its just two opamp stages and one small filter package per sense leg (plus one 4046 for its VCO to drive the filter IC's). As with anything being clocked at high frequencies, attention to layout, grounding and decoupling is required. With attention to those details, I have obtained excellent performance from these filters even on the likes of a protoboard.
With a non ground referenced L1/C1, things become a bit more complicated. Isense can be easily performed using an isolated winding on a small core, however, Vsense becomes quite problematic. I have considered several options with regard to this over the past months, but I have yet to settle on a solution I feel comfortable with. I can discuss those considerations in greater detail if you desire, however, most options use some form of the above discussed circuits with additions/modifications to the Vsense leg, making the amplifier and filter circuitry discussed above a good staring point for consideration.
A control method I am considering requires control of the phase and resonant frequency of both the grenade and inductor loops, as well as amplitude control of at least the inductor loop (relative to the grenade). This requires I and V sense of both the grenade and inductor loops. To simplify initial experiments, I plan to ground reference both grenade and inductor (there was at least one schematic presented on the past threads that did show both inductor and grenade ground referenced).
PW
Thanks PW,
so it is doable, both grounded as un-grounded.
I see the LTC1569-7 is not available at the moment, probable due to the chip shortage, a problem which goes for more advanced chips lately.
I will see if i can transform my setup to a grounded one using one of those mentioned schematics and what influence this has on the signals.
Itsu.
Quote from: Itsu on 2022.02.10, 09:06:21
Thanks PW,
so it is doable, both grounded as un-grounded.
For the un-grounded systems, all I have are a few concepts that need to be investigated. Watching videos with corona being drawn to screwdrivers makes me think that common mode voltage and noise is going to be a significant issue. I have considered several solutions that range from use of a basic diff amp at the front-end to more isolated systems using opto or galvanic isolation. However, having looked at the specs for a few "off the shelf" isolated solutions, I have doubts as to whether their hold-off capability is sufficient in this operating environment.
I have considered sensing only the current flowing in the loop using an isolated pickup and having the circuit adjust for max current in that loop as a way to stay in resonance. I even made a few proof of concept tests on such a system. However, not only do I want to be able to monitor and maintain a given I/V phase relationship in the individual grenade and inductor loops, I want to be able to select and maintain a given phase relationship between the I and/or V of those two loops. This will require four sense inputs (2 Isense and 2 Vsense). I decided first attempts would be with both the grenade and inductor ground referenced, which allows empirical I and V values to be collected, prior to considering lifting the grounding on one or both loops. But, when crossing that bridge, a diff amp input would be a first consideration.
QuoteI see the LTC1569-7 is not available at the moment, probable due to the chip shortage, a problem which goes for more advanced chips lately.
Digikey and Mouser have them in stock (as do a few Ebay sellers from China). Search using only "LTC1569" or with the full monty such as "LTC1569CS8-7". Just make sure you get the "-7" version, not the "-6" (-6 is only good to 64Khz).
The reason I am considering using these in my initial experiments is that I need four filters with good filter to filter thermal stability/tracking and I already have a few of these on hand. For your initial tests, you could use a dual or quad opamp configured as a 4th or 8th order LP. If you go the analog route, be sure to use low tolerance resistors and capacitors with a low Tc (NPO, etc). Good thermal stability would be my primary concern because static phase errors between filters can be trimmed out elsewhere in the system.
In the system you are proposing, inductor resonance will determine your P-P frequency. Will you then be required to adjust the cap or inductance in the grenade loop to chase its resonance?
QuoteI will see if i can transform my setup to a grounded one using one of those mentioned schematics and what influence this has on the signals.
Itsu.
Please let us know how grounding affects your circuit.
I hope Verpies will comment on all of this as well, particularly with regard to Vsense in this environment.
PW
Quote from: picowatt on 2022.02.10, 12:43:02
I hope Verpies will comment on all of this as well, particularly with regard to Vsense in this environment.
Whatever the solution, it needs to avoid capacitive coupling and that means differential sensing (preferably isolated from ground) with short connections.
I have an original solution to this problem for ~$20 if you can come up with an equally cheap yet fast PWM modulator (~10MHz with sub nanosecond jitter) 8)
P.S.
Yes, "PWM modulator" is a redundant phrasing but I was afraid that "PW modulator" would not be understood by everyone reading it.
Quote from: picowatt on 2022.02.10, 12:43:02
For the un-grounded systems, all I have are a few concepts that need to be investigated. Watching videos with corona being drawn to screwdrivers makes me think that common mode voltage and noise is going to be a significant issue. I have considered several solutions that range from use of a basic diff amp at the front-end to more isolated systems using opto or galvanic isolation. However, having looked at the specs for a few "off the shelf" isolated solutions, I have doubts as to whether their hold-off capability is sufficient in this operating environment.
I have considered sensing only the current flowing in the loop using an isolated pickup and having the circuit adjust for max current in that loop as a way to stay in resonance. I even made a few proof of concept tests on such a system. However, not only do I want to be able to monitor and maintain a given I/V phase relationship in the individual grenade and inductor loops, I want to be able to select and maintain a given phase relationship between the I and/or V of those two loops. This will require four sense inputs (2 Isense and 2 Vsense). I decided first attempts would be with both the grenade and inductor ground referenced, which allows empirical I and V values to be collected, prior to considering lifting the grounding on one or both loops. But, when crossing that bridge, a diff amp input would be a first consideration.
Digikey and Mouser have them in stock (as do a few Ebay sellers from China). Search using only "LTC1569" or with the full monty such as "LTC1569CS8-7". Just make sure you get the "-7" version, not the "-6" (-6 is only good to 64Khz).
The reason I am considering using these in my initial experiments is that I need four filters with good filter to filter thermal stability/tracking and I already have a few of these on hand. For your initial tests, you could use a dual or quad opamp configured as a 4th or 8th order LP. If you go the analog route, be sure to use low tolerance resistors and capacitors with a low Tc (NPO, etc). Good thermal stability would be my primary concern because static phase errors between filters can be trimmed out elsewhere in the system.
In the system you are proposing, inductor resonance will determine your P-P frequency. Will you then be required to adjust the cap or inductance in the grenade loop to chase its resonance?
Please let us know how grounding affects your circuit.
I hope Verpies will comment on all of this as well, particularly with regard to Vsense in this environment.
PW
PW,
QuoteIn the system you are proposing, inductor resonance will determine your P-P frequency. Will you then be required to adjust the cap or inductance in the grenade loop to chase its resonance?
In the original Ruslan setup, there was as i understood it no resonance on the Grenade coil and i have to recheck the Stalker circuit to see it is needed there.
Itsu
Quote from: verpies on 2022.02.10, 19:24:16
Whatever the solution, it needs to avoid capacitive coupling and that means differential sensing (preferably isolated from ground) with short connections.
I have an original solution to this problem for ~$20 if you can come up with an equally cheap yet fast PWM modulator (~10MHz with sub nanosecond jitter) 8)
P.S.
Yes, "PWM modulator" is a redundant phrasing but I was afraid that "PW modulator" would not be understood by everyone reading it.
QuoteYes, "PWM modulator" is a redundant phrasing but I was afraid that "PW modulator" would not be understood by everyone reading it.
:)
Quote from: Itsu on 2022.02.11, 09:03:38
PW,
In the original Ruslan setup, there was as i understood it no resonance on the Grenade coil and i have to recheck the Stalker circuit to see it is needed there.
Itsu
Itsu,
With regard to the Stalker schematic, I understood all items marked with an asterisk as needing to be "adjusted" or "tuned". In that schematic, there is a HV cap across the grenade, just prior to the "output choke", and it is marked with an asterisk.
What method did you use to select the value of the cap across the grenade winding?
PW
Yes, the Grenade needs to be tuned, but not necessarily for the same resonance as the inductor as in my experience, it is(?) impossible to have both the Inductor and the Grenade tuned to the same resonance frequency.
Vasik mentioned that a 2:1 resonance was used also to overcome that dual resonance problem, i tried both a single resonance point (24Khz), but did not succeed, as the 2:1 relation.
But all in all, my Grenade output was to low overall (should be 300 to 400V DC after rectification).
Itsu
Quote from: Itsu on 2022.02.11, 14:51:00
Yes, the Grenade needs to be tuned, but not necessarily for the same resonance as the inductor as in my experience, it is(?) impossible to have both the Inductor and the Grenade tuned to the same resonance frequency.
Vasik mentioned that a 2:1 resonance was used also to overcome that dual resonance problem, i tried both a single resonance point (24Khz), but did not succeed, as the 2:1 relation.
But all in all, my Grenade output was to low overall (should be 300 to 400V DC after rectification).
Itsu
Hi Itsu I don't want to faff about here so here goes if the Katcher is running at 1.8 mhz how on EARTH are you going to shuve that through the grenade ? it's impossible to de modulate it with the push pull running at 24 khz!
you need the missing link perhaps O0 O0