Conventional (non-OU, but related) electronic circuit problem

[Verpies]

Hi Itsu, your circuit drifts because of component values change with component tolerances to temperature,

No, no - this circuit does not drift in frequency.
The circuit works well and locks to the LC resonance frequency over a wide range of frequencies.
See this video where Itsu purposely saturates the core of the inductor with a permanent magnet in order to change the overall LC resonance frequency.  Note that the PLL tracks these frequency changes quite well.

The problem with it is that the front end circuit which conditions the i & v feedback signals is imperfect because it introduces phase shifts. The PLL then locks to these incorrect phase shifted signals quite well.

This thread is not about improving the operation of the PLL (which works very well) but about improving the noisysine-to-square converters in the front end, which do not behave like zero-crossing detectors because of their design with 2 level hysteresis around the zero line - not because of their thermal drift.

The noise comes mainly from low-resistance CSR (including its amplifier, if any) and external noise sources associated with the externally driven LC circuit.  The source of this noise is actually off-topic here except for its frequency characteristics as posed in Picowatt's question.

I promise you that once these front-end kinks are ironed out and PCB designed, there will be another thread about the applications of the entire circuit and its performance.

[Itsu]

Itsu,

this might be irrelevant but I remember Stalker saying that you not supposed to load push pull,
so just a simple "frequency lock" should be enough.

You can check induction heater schematics, they usually have nice voltage/current sensors schematics which you can reuse in your setup.

Regards,
Vasik

Thanks Vasik,      good to know and perhaps usable in the follow up when we have solved this noise problem.

Itsu

[Itsu]

Itsu,

When you say "frequency independent", is there a range of permissible operation that you can specify?  For example, does the desired frequency of operation vary over a limited range (i.e., +/- some small percentage) or are you wanting something with a very wide detection bandwidth?

Is the noise random or are there components that may be synchronous with or harmonically related to the detected signal?

Is the signal to noise ratio depicted in your scope shots representative of the worst case S/N ratio encountered?

PW

PW, see verpies his answer 

Itsu

[Itsu]

Hi Itsu, your circuit drifts because of component values change with component tolerances to temperature, the problem is the frequency would have to track this drift to keep LC in resonance or the other way is to use a xtal frequency stable circuit (digital) to get your 15khz and then use an LC circuit to obtain resonance.

There is always a way to do what your trying to do, other than drawing energy and heating up the device will end in thermal runaway.

Regards Sil

PS there is a more simple way.

I think you are referring to my "not working PLL video" i showed in this post to Vasik:  https://www.overunityresearch.com/index.php?topic=4248.msg97569#msg97569 which is not the topic of this discussion.

Itsu

[Itsu]

Yes, the asymmetrical power supply was needed to create the sawtooth waveform at the CT input (pin5) of the TL494 chip.

That negative -1.25V supply was just reused in the noisysine-to-square wave converters in the front-end, to accept bipolar feedback signals.  A fully symmetrical ± power supply would have been better, but it was just too much hassle at the time.
Automatic zero level adjustment, as depicted in this TI Application Note, would work, too, and with AC coupling and ½V_CC virtual ground a unipolar/single supply would be sufficient.

It would be nice for the guys to see a scopeshot of the voltage waveform at TL494.pin5, with respect to ground (even in the TL494 test configuration depicted in its datasheet on pg.8).

Here a screenshot of an other working TL494 running at 15V with its pin 5 signal (green) and one of its output signal (purple) referenced to ground:


Itsu

[Verpies]

Here a screenshot of an other working TL494 running at 15V with its pin 5 signal (green) and one of its output signal (purple) referenced to ground:

I would like to add that the waveforms appearing at pins 6 & 7 of the 74HC4046 chip, have negative excursions below ground, which is the reason why a negative supply is needed for the op-amps U3a and U3b.  This info is off-topic.

[AlienGrey]

Can I just run this other idea across you, perhaps the best idea is the Igorek idea where it starts in the kacher coil.
He drives the primary with one frequency and modulates the secondary with another frequency so you have 1/2 wave and 1/4 wave taking off so to speak.

You still need to phase lock it with a 4046 but it becomes much simpler the way he did it over on Vasics thread.

Sil

[picowatt]

PW, see verpies his answer 

Itsu

Itsu,

Low pass filtering to reduce harmonics and HF noise is of course a first thought.  However, requiring the lock-in range to be the full bandwidth of the HC4046, or the TL494, is going to complicate any filter or tracking filter design. 

Can the lock-in range instead be made relatively narrow with the center frequency of that range adjusted as required throughout the desired bandwidth?

In other words, are the values of L1 and C1, and their approximate resonant frequency, known beforehand so that the center frequency can be set to that approximation and the lock-in range limited to some narrow bandwidth around that center frequency?

How critical is response time?  Can long period averaging of the phase correction be tolerated?

PW

Added:

Is the S/N ratio depicted in your scope shots represent the worst case S/N ratio you have to work with?

[picowatt]

If you have any suggestions about a faster P-P PWM chip, post them in the New Developments thread for now.

Verpies,

Apparently, I do not have permission to view or post in that thread...

PW

[partzman]

Itsu,

If you haven't already found a solution, you might try removing C1 and reducing R1 to a range of 0-50 ohms.  Disconnect D1.D2 but leave D3,D4 connected and use the asymmetrical supplies.  In simulation, this produces a very small symmetrical phase delay on the rising and falling edges which might be tolerable.  This also removes any phase changes with frequency as C1 would create.

Regards,
Pm

Edit: Added sim for clarity.

[Itsu]

Itsu,

Low pass filtering to reduce harmonics and HF noise is of course a first thought.  However, requiring the lock-in range to be the full bandwidth of the HC4046, or the TL494, is going to complicate any filter or tracking filter design. 

Can the lock-in range instead be made relatively narrow with the center frequency of that range adjusted as required throughout the desired bandwidth?

In other words, are the values of L1 and C1, and their approximate resonant frequency, known beforehand so that the center frequency can be set to that approximation and the lock-in range limited to some narrow bandwidth around that center frequency?

How critical is response time?  Can long period averaging of the phase correction be tolerated?

PW

Added:

Is the S/N ratio depicted in your scope shots represent the worst case S/N ratio you have to work with?

PW,

The initial Ruslan design devices were centered around the 17, 27, and 37KHz resonance frequencies and my initial one was 17KHz i think and the last one 24Khz, but i also saw designs with 12Khz, so i would say that the range would be between 10 to 50KHz.

But it can be that verpies has a more universal approach in mind with the limit only set by some components in use like the TL494 with its 300 to 500KHz limit.
I am sure verpies will come back to you on that.

Concerning the response time and S/N ratio, those are still unknowns to me as it was not implemented yet into a real environment (Ruslan).

Itsu

[Itsu]

Itsu,

If you haven't already found a solution, you might try removing C1 and reducing R1 to a range of 0-50 ohms.  Disconnect D1.D2 but leave D3,D4 connected and use the asymmetrical supplies.  In simulation, this produces a very small symmetrical phase delay on the rising and falling edges which might be tolerable.  This also removes any phase changes with frequency as C1 would create.

Regards,
Pm

Edit: Added sim for clarity.

PM,

no, no solution found yet,   so i will try your suggestions tonight.

Itsu

[Verpies]

I have been thinking of the following method to find the time of the zero crossing, which takes advantage of the fact that two neighboring hemicycles which straddle the zero-line most equally and sum closest to zero are the most likely "place" where the zero-crossing occurs.

Take a look at the following scopeshot which depicts the sum of a LF and HF sine waves ( the HF simulates the noise ).
This composite signal crosses the zero-line at multiple times, which makes it hard to find the true time of the LF component's zero-crossing without using an LPF and its frequency dependent phase delay.

I have colored two neighboring hemicycles which straddle the zero-line in red color when they sum close to zero^* ...and in blue color when they don't sum close to zero.  You must magnify the scopeshot to see these colors well.

Notice that the hemicycles which straddle the zero-line equally and sum to zero (red) are the closest ones to the zero-crossing of the LF sine wave and that condition is independent of the frequency of the superimposed HF signal.


^* The area below the zero-line counts as negative and the area above the zero-line counts as positive. When these two areas are equal then they sum to zero.

[Itsu]

PM,

no, no solution found yet,   so i will try your suggestions tonight.

Itsu

PM,

the simulation shows identical signals as your simulation (of course) see first picture, but when building this on a breadboard i still have the phase shift, see screenshot below.

Itsu

[Verpies]

...but when building this on a breadboard i still have the phase shift, see screenshot below.

Could you make another scopeshot with a 3^rd trace which shows the voltage at the "+" input of the op-amp ...with the same zero-line as the "-" input ?

[partzman]

PM,

the simulation shows identical signals as your simulation (of course) see first picture, but when building this on a breadboard i still have the phase shift, see screenshot below.

Itsu

Well that's a disappointment!  Maybe Verpies suggestion will shed some light on the problem.

Pm

[Itsu]

Could you make another scopeshot with a 3^rd trace which shows the voltage at the "+" input of the op-amp ...with the same zero-line as the "-" input ?

The purple trace is on the pin 3 (+) of the opamp:

[Verpies]

So the question is why that purple trace goes only -400mV below ground (it should be around -600mV - the full diode voltage drop) while the output of the op-amp is over -1V below ground? 
The 10:11 resistive voltage divider should allow over -900mV at that point.
Diodes, diodes, diodes ...and capacitance.  Ditching the diodes and adjusting the voltage divider to limit the voltage at the "+" input to be below the amplitude at the "-" input, would require a symmetrical supply rails or virtual ground at ½Vcc.

[picowatt]

PM,

the simulation shows identical signals as your simulation (of course) see first picture, but when building this on a breadboard i still have the phase shift, see screenshot below.

Itsu

Itsu,

My 2 cents...

With asymmetrical supplies, the current thru R2/R3, and hence the forward voltage of D2/D3, will be different for the two output polarities.  This produces an asymmetrical threshold voltage at the input.  The breadboarded circuit appears to be working as would be expected.  It is the simulator that seems to be in error.  Perhaps the simulator is modeling the diode forward voltage as a fixed voltage regardless of forward current (which it is not).   

Even with symmetrical supplies, I would think the use of D2/D3 would create excessive hysteresis for this app.  Are you wanting wanting the large hysteresis to help deal with the noise issue?

As well, diodes are not all that great for setting reference voltages...

PW

[Itsu]

Be aware that my bench circuit is modeled after Partzman his latest simulation circuit with the exception that i still have the 100K trimmer for R3.

So R1 is 22 Ohm, R2 is 10K and R3 is unknown as the signals do not change while going to its (R3) range.

Itsu

[Itsu]

Ok, the fact that my R3 was not changing the signals made me double check the circuit and it turned out that this R3 was not attached to ground 

I probably removed it when changing from a dual opamp (both amps working) setup to a single amp operation we have now.
   
After fixing this ground issue i now have some signal change when turning this pot.

I have returned the circuit to the original one, so with the 4 diodes and 10K input R1 like below.

The phase shift is still there but much less.

Itsu

[Itsu]

This screenshot is from the circuit after Partzman his mod (R1 = 22 Ohm, D1 and D2 removed):

(His D1 / D2 in the sim, my D3 and D4 on the breadboard / diagram).


Seems now very close to the sim signals.

[Verpies]

The phase shift is still there but much less.

Eventually, you can eliminate the phase shift by setting the two hysteresis thresholds differently, but only with non-noisy input signal.

[partzman]

This screenshot is from the circuit after Partzman his mod (R1 = 22 Ohm, D1 and D2 removed):

(His D1 / D2 in the sim, my D3 and D4 on the breadboard / diagram).


Seems now very close to the sim signals.

Ahh, that's better!   

Pm

[picowatt]

Ok, the fact that my R3 was not changing the signals made me double check the circuit and it turned out that this R3 was not attached to ground 

I probably removed it when changing from a dual opamp (both amps working) setup to a single amp operation we have now.
   
After fixing this ground issue i now have some signal change when turning this pot.

I have returned the circuit to the original one, so with the 4 diodes and 10K input R1 like below.

The phase shift is still there but much less.

Itsu

Itsu,

You have reduced the error by reducing the hysteresis, but with the different Vfwd's on D5 an D6 due to the assymetrical rails, this error will vary as you vary the amount of hysterisis.

My suggestion would be to operate the comparators on just the 6 volt rail, generate a mid-rail reference (buffered voltage divider) to use for signal ground connections, and AC couple the inputs.  Your waveforms will be symmetrical and that symmetry will not change as you adjust hysteresis.     

Regarding the noise issue, I would add some analog signal conditioning in front of the comparators.  Consider adding an AC coupled variable gain stage and a LP filter in front of the comparators.  What order of filter you will need is dependent on the amount and type of noise you are dealing with (a 4th to 8th order filter comes to mind).  With a sufficiently slow loop filter at the PLL, truly random noise (i.e., white noise) will average out to a zero phase error.  Non-random noise (i.e., spurious or synchronous signals) can be a bit more problematic, but with a LP filter of sufficient order, adjustment of comparator hysteresis, and a slow PLL loop filter, their contribution to phase errors will be reduced significantly.

Using identical analog front ends (i.e., the same gain, filter, and comparator circuits) will null out the phase shifts caused by these stages.

Fixed frequency analog filters will need to be modified for operation at each of the various frequencies you mentioned.  If you need truly variable frequency capability, there are some switched capacitor options available to use as tracking filters, but at frequencies greater than 100KHz, these options become limited and more complex.  However, I would think variable frequency operation over a large bandwidth would be unnecessary unless you plan to somehow vary L1 or C1 by large amounts during operation.  Modifying the passband of fixed filters for each of the desired frequencies of operation would be a simpler solution.

Using diff amps at the front-end would allow detection of I and V with a non-ground referenced L1/C1 (i.e., using a sense coil and a matched pair of voltage dividers for I and V detection).

I would also consider adding an adjustable mono stable between one of the comparator outputs and its PLL input to allow for adjustment of I/V phase.

You mention Ruslan type circuits.  However, can you provide more details as to why L1 and C1 are being driven by an opamp in the OP schematic?
 
PW