Q measurement methods

Author Topic: Q measurement methods (Read 1458 times)

Verpies	Re: Q measurement methods « Reply #125 on: 2026-05-28, 20:49:57 »
Group: Administrator Hero Member Posts: 4856	What happens when you simulate this in LTspice ?

Itsu	Re: Q measurement methods « Reply #126 on: 2026-05-28, 22:15:42 »
Group: Moderator Hero Member Posts: 4848	Not much if i look at the red and light blue traces, they are around 6mVpp: Itsu

Verpies	Re: Q measurement methods « Reply #127 on: 2026-05-28, 22:59:30 »
Group: Administrator Hero Member Posts: 4856	The bias resistors were calculated for the BF245 JFET model. The B grade preferably.

Itsu	Re: Q measurement methods « Reply #128 on: 2026-05-29, 09:16:05 »
Group: Moderator Hero Member Posts: 4848	OK, i found a BF245B LTspice model: Looks better, having 678mVpp at the light blue probe and comparator output

Verpies

Re: Q measurement methods « Reply #129 on: 2026-05-29, 13:51:05 »

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Quote from: Itsu on 2026-05-29, 09:16:05

Looks better, having 678mVpp at the light blue probe and comparator output

The gain can still be increased with different biasing. Perhaps someone else could help to calculate it ...?
e.g.: R5→220Ω to 470Ω, R3→2kΩ to 5kΩ or something in-between. C2→1µF to accommodate lower cascode frequencies (kHz). When adjusting these values, have LTspice make a plot of the voltage gain vs. frequency (over the 1kHz - 10MHz span) measured at J1.drain.
Additionally, I think that R4 can be increased to 100MΩ and C4 can be eliminated or substituted with a protective resistor. The C7 should be a high-ESR cap (yes - unusual) and can change R12→10MΩ. Also, it would be beneficial to swap the inputs of the comparator and apply the signal coming from R7 and the R12 hysteresis feedback to the noninverting input so C5 only stabilizes the reference voltage at the inverting input and doesn't shunt the hysteresis feedback to ground (with this change, a low-ESR C7 doesn't hurt anything ...and even hepls)
Some low-C clamping diodes at the junction of R7,R8,R9 might be needed if the voltage at this node gets too high at high input signal levels.

If the comparator's kickback still backpropagates to the input in a real circuit then increase R7 (the one thing LTspice cannot simulate).
Also, to keep the input impedance high, the J1 and J2 and surrounding resistors/caps, should be connected in the air using the "dead bug" style with short legs.
Generally, the amplifier still needs design work.

P.S.
The BF245 transistors have a wide parameter spread due to high tolerances of the old manufacturing process. The C version - the highest spread. The A version - the lowest spread, but it is a lottery with all of them (just the odds differ).
The gain of the JFET amplifier should be judged by the amplitude at the red probe (J1.drain) because J3 is just a source follower for the comparator kickback isolation.

Itsu	Re: Q measurement methods « Reply #130 on: 2026-05-29, 20:28:10 »
Group: Moderator Hero Member Posts: 4848	OK, i here first made a basic plot of the voltage gain (drain J1 (node n003) / top R4 (node n010) over a 1kHz to 10MHz range with a highlight on our used frequency of 2143kHz: So IMO we presently have a 67.95dB gain at 2143kHz.

Verpies

Re: Q measurement methods « Reply #131 on: 2026-05-29, 20:32:54 »

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Quote from: Itsu on 2026-05-29, 20:28:10

OK, i here first made a basic plot of the voltage gain (drain J1 (node n003) / top R4 (node n010) over a 1kHz to 10MHz range with a highlight on our used frequency of 2143kHz:

Yes, keep monitoring this plot at J1.drain as you vary the surrounding component values.

Sanity Checks (without input signal):

Real resistor tolerance: With R7 and R12 removed, the DC voltage measured between the junction of R8/R9 and the junction of R11/R10 should be zero (or very close to zero) - if not, then trim these resistors.
V(J1.gate) to GND = 2.27V. If your voltmeter reads anything other than 2.25 .. 2.30V then there is something wrong. This is set entirely by the R1/R2 voltage divider: 15V × 10k/(56k+10k) = 2.273 V.
V(J2.source) to GND: The healthy target window with R5 = 1 kΩ is 0.8V .. 2.0V. Anything outside of this range is suboptimal. This is the most informative single measurement in the circuit. It directly encodes drain current: Id = V(J2.source) / R5. With R5 = 1 kΩ the arithmetic is trivial - voltage in volts equals current in milliamps.
V(J1.drain) to V(J2.drain) =
8.72V : Healthy. J1 has ample Vds
7.19V : Healthy. Nominal operating point.
4.69V : Still comfortable
1.90V : Barely working. Coming out of saturation. Reduced gain
< 1.0V : Failed cascode.

Itsu

Re: Q measurement methods « Reply #132 on: 2026-05-29, 21:12:31 »

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Quote

Yes, keep observing this plot as you change the component values.

OK, so when doing the first part:

Quote

e.g.: R5→220Ω to 470Ω, R3→2kΩ to 5kΩ or something in-between. C2→1µF to accommodate lower cascode frequencies (kHz). When adjusting these values, have LTspice make a plot of the voltage gain vs. frequency (over the 1kHz - 10MHz span) measured at J1.drain.
Additionally, I think that R4 can be increased to 100MΩ and C4 can be eliminated or substituted with a protective resistor.

Changing 1 component at a time:

Base voltage gain at 2143kHz was: 67.95dB
R4 from 10 to 100M: 67.95dB
C4 remove: 0dB
R5 from 1K to 220 Ohm: 30.91dB
R5 from 1K to 470 Ohm: 64.90dB
R3 from 3.9K to 2K: 68.56dB
R3 from 3.9K to 5K: 67.56dB
C2 from 100nF to 1uF: 67.95dB (lower frequency 1kHz went from 59.4dB to 68.94dB, changeover point around 11kHz)

Not sure why removing C4 stops everything.

Itsu

Verpies

Re: Q measurement methods « Reply #133 on: 2026-05-29, 21:19:12 »

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The gate of a real BF245 JEFT is very sensitive. Even an ohmmeter can damage it.
Input clamping is advised for higher input signal amplitudes (e.g.: current limiting resistor + sdiodes like the BAT68 with 0.5pF ...or BAT15-03W with 0.25pF ...or better yet: HSMS-2810 with 0.1pF ) ...but we will deal with that later.

The gate of a JFET is normally a reverse-biased P-N junction (like a diode) that has leakage current in the pA range. The BF245B datasheet gives Igss ≤ 1 nA under worst-case test conditions (large reverse voltage, elevated temperature).
if your quiescent (no input signal) DC measurements indicate V(J2.source) to GND that is higher than expected AND V(J2.gate) to GND which is > 50 mV above zero, then the two observations are linked - the damaged gate junction is the root cause of both.

Itsu

Re: Q measurement methods « Reply #134 on: 2026-05-29, 21:47:39 »

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Doing the second part:

Quote

change R12→10MΩ. Also, it would be beneficial to swap the inputs of the comparator and apply the signal coming from R7 and the R12 hysteresis feedback to the noninverting input so C5 only stabilizes the reference voltage at the inverting input and doesn't shunt the hysteresis feedback to ground (with this change, a low-ESR C7 doesn't hurt anything ...and even hepls)

I get:

Voltage gain at 2143kHz at OUTPUT / n004 (R7, R8, R9) is -110,22dB
Change R12 to 10M: 45.56dB

Comparators + and - swapped OUTPUT / n005 (R7, R8, R9) is -103.72dB
Change R12 to 10M: 45.50dB

Changing C7 ESR does not influence these latest measurements.

I don't think these last measurements are useful as there is not really a gain (going from sine to square).

Itsu

Verpies

Re: Q measurement methods « Reply #135 on: 2026-05-29, 22:24:58 »

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Quote from: Itsu on 2026-05-29, 21:47:39

Doing the second part:

Please post the screenshot of the changed schematic.

Quote from: Itsu on 2026-05-29, 21:47:39

I don't think these last measurements are useful as there is not really a gain (going from sine to square).

Yes, measuring the comparator is like comparing apples to oranges because the input is analog and the output is digital. The comparator still has a gain that is listed in its datasheet (AFAIR gain=100000).
The change made to the comparator's circuit (swapping its inputs) might not make much difference in the simulation, but it will make a difference in the real circuit.

Itsu	Re: Q measurement methods « Reply #136 on: 2026-05-30, 09:47:49 »
Group: Moderator Hero Member Posts: 4848	Swapped comparators inputs: We see a change in duty cycle, not 50% anymore Now also changed R12 to 10M: Now we see a very small amplitude (476nV) of the output signal. So swapping the comparators inputs has a negative effect on the output signal i did not notice during the frequency plot yesterday.

Verpies	Re: Q measurement methods « Reply #137 on: 2026-05-30, 13:15:45 »
Group: Administrator Hero Member Posts: 4856	Quote from: Itsu on 2026-05-30, 09:47:49 Swapped comparators inputs: That's why it is important to post schematics after topo changes. See the corrections in red color: Q measurement methods zztop.png (22.97 kB, 969x392 - viewed 37 times.)

Itsu	Re: Q measurement methods « Reply #138 on: 2026-05-30, 15:58:22 »
Group: Moderator Hero Member Posts: 4848	Thanks, stupid mistake, I surely need to stay off the decaf in the morning. It does not make any difference at the output indeed, not with R12 as 1.2M nor with 10M. I found a TLV3201 model, so i used it in the sim: R12 = 10M, shown is the output in green and the non-inverted input (+) in blue. Itsu

Verpies	Re: Q measurement methods « Reply #139 on: 2026-05-30, 20:43:45 »
Group: Administrator Hero Member Posts: 4856	Do the present values of R3 and R5 pass the DCV sanity checks and give you maximum voltage gain at J1.drain ?

Itsu	Re: Q measurement methods « Reply #140 on: 2026-05-30, 21:23:21 »
Group: Moderator Hero Member Posts: 4848	You mean in the sim? If so, yes, 1.25mA through R5.

Verpies	Re: Q measurement methods « Reply #141 on: 2026-05-30, 23:15:20 »
Group: Administrator Hero Member Posts: 4856	Quote from: Itsu on 2026-05-30, 21:23:21 You mean in the sim? Yes. What do you get between V(J1.drain) to V(J2.drain) ?

Itsu	Re: Q measurement methods « Reply #142 on: 2026-05-31, 08:56:36 »
Group: Moderator Hero Member Posts: 4848	Voltage between J1.drain to J2.drain is 6.537V This is still with no input signal and removed R7 as in your post #131 above.

Verpies	Re: Q measurement methods « Reply #143 on: 2026-05-31, 14:18:06 »
Group: Administrator Hero Member Posts: 4856	Quote from: Itsu on 2026-05-31, 08:56:36 Voltage between J1.drain to J2.drain is 6.537V Can you get it above 7V ?

Itsu	Re: Q measurement methods « Reply #144 on: 2026-05-31, 15:32:47 »
Group: Moderator Hero Member Posts: 4848	Yes, by lowering R3 from 3.9K to 3.5K it becomes 7.03V (1.253mA) with a voltage gain of 68.08dB at 2143kHz. Lowering R3 further to 2.1K, the J1.drain to J2.drain voltage becomes 8.77V with a voltage gain at 2143kHz of 68.5dB.

Itsu

Re: Q measurement methods « Reply #145 on: 2026-06-01, 22:06:22 »

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I build the amplifier part on a pcb according to the "dead bug" method:

This circuit schematic is like this (using BF245C's, and the voltages in red are measured without input signal J1 gate and J2 source to ground):

When applying the input signal (100mVpp at 2143kHz), i get these signals (blue input from FG, yellow signal on J1 drain and purple is at output (R7):

To compare the signals with the LTspice sim, here the same circuit as in real, but with BF245B's:

Sim: Real:

Blue 100mVpp 109mVpp
Yellow 442.1mVpp 498.8mVpp
Purple 403.7mVpp 455.6mVpp

One thing i do not understand is that the Sim shows a ~12V DC offset on the purple trace like it does with the yellow trace, but the real circuit measurement show this DC offset ONLY on its yellow trace (therefor the yellow probe is set in AC coupling).

Why does the Sim shows this DC offset as there is a DC blocking capacitor (C5) which should block this DC?

Answer, apparently LTspice needs to know that the output has a high (MOhms) reference to ground, so when adding a 10MOhm resistor from OUTPUT to ground it loses the DC offset.

Amplifier gain input to output calculated (https://circuitdigest.com/calculators/decibel-db-calculator)

shows 12.13dB for the sim, and 12.42dB for the real circuit.

Itsu

« Last Edit: 2026-06-02, 13:03:54 by Itsu »

Itsu	Re: Q measurement methods « Reply #146 on: 2026-06-02, 09:47:53 »
Group: Moderator Hero Member Posts: 4848	Updated the above post

Itsu

Re: Q measurement methods « Reply #147 on: 2026-06-02, 20:04:44 »

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When i use verpies his ring down circuit to produce the ring down signal of the LC tank circuit, and use the current probe plus its amplifier to pick up this ring down signal, which then is fed into the Jfet amplifier, i get these Jfet amplifier in- and output signals:

Purple is the input signal coming from the current probe amplifier and blue is the output signal from the Jfet amplifier, taken at R7.

This output signal seems ready to be fed into the TLV3202 comparator for further processing to a square wave.

Itsu

Verpies

Re: Q measurement methods « Reply #148 on: 2026-06-02, 20:11:50 »

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Quote from: Itsu on 2026-06-02, 20:04:44

When i use verpies his ring down circuit to produce the ring down signal of the LC tank circuit, and use the current probe plus its amplifier to pick up this ring down signal, which then is fed into the Jfet amplifier, i get these Jfet amplifier in- and output signals:

You could also use it to pick up the voltage signal from the LC circuit directly. But JFET input protection becomes an issue (especially the one that forward biases the gate-source).

Quote from: Itsu on 2026-06-02, 20:04:44

This output signal seems ready to be fed into the TLV3202 comparator for further processing to a square wave.

So add the output of the TLV3202 to that scopeshot.

Itsu	Re: Q measurement methods « Reply #149 on: 2026-06-02, 22:04:42 »
Group: Moderator Hero Member Posts: 4848	So i completed to add the comparator circuit to the dead bug pcb, and added the comparators output to the screenshot in yellow: Signals are somewhat "dynamic" and glitchy, perhaps because we are ringing at 2.3MHz. The "end" of the ringing period when signals are becoming small present a problem for the comparator as it starts to "fade out": Anyway, we're getting there slowly. Itsu