What filter topology would you suggest for the least variability of phase delay vs. frequency (grp dly), in the passband ?
I'd consider an 8th order lowpass using a quad opamp with four unity gain Sallen Key filters (depending on the type of noise and the S/N ratio, a lower order filter may suffice). Group delay will indeed be ugly, but if the two filters are well matched, a phase trim somewhere in the system should allow mismatches to be trimmed out. The type of filter selected will depend on the makeup of the noise to be rejected.
The Bessel filter produces a milder slope with regard to group delay versus frequency as the cutoff frequency is approached. However, an 8th order Bessel will only give you about 30dB of rejection at the nearest harmonic. The 8th order Butterworth has a much steeper group delay slope as cutoff is approached, but will provide more like 60dB of rejection of the nearest harmonic.
Because both inputs will see the same frequency, the phase errors should be consistent and, as above, able to be trimmed somewhere else in the system.
The advantage to using analog filters is that they are low noise and relatively easy to implement. The disadvantage is that components will need to be low tolerance with low Tc and in order to change the frequency, components will need to be changed for each desired frequency of operation.
From a hardware standpoint, a much simpler solution is to use a switched cap filter. One that comes to mind is the 10th order lowpass filter LTC1569-7 (they are a bit pricey @$15 each, but if you are willing to wait for shipment from China, I have seen them go for $5 or so). The advantage of using this filter is that they are easily tuned to the desired frequency via an external clock, with no hardware changes required, and are usable up to just over 300KHz. They have a nearly constant group delay at around 18us that only changes to 17us around the cutoff frequency (and with excellent chip to chip matching). They have a very steep rolloff above the cutoff frequency and could, with relative ease, be incorporated as a tracking filter.
They do require a clock (32X) and will need an anti-alias filter on the front-end and a LP at the output to remove residual clock noise. However, because the clock is 32X the cutoff frequency, these can typically be low order RC filters.
Yes, but only if the noise characteristics on both channels are identical. In Itsu's experience the signal from the CSR is much more noiser than the voltage signal.
Regardless of which filter type is used, I do not believe that the "flavor" or amount of noise will have an influence on the phase error through the two filters. The frequency of interest will be the same for both filters and group delay will be somewhat matched between the filters. As long as low Tc components are used, any phase error difference between the filters should be rather static and able to be trimmed out somewhere in the system.
Regarding Itsu's greater noise at the Isense leg, this is why I suggest a proper low noise amplifier in front of the filters. Not only will this reduce noise, but it will allow Rsense to be reduced to more realistic values.
An advanced yet inexpensive idea to minimize the common mode noise ingress at the input. I forgot about it. Thanks for the reminder.
I would consider a three opamp IA configuration at the front-end (yes Itsu, even more complexity...). The advantage is the ease with which gain can be adjusted without messing with the CMRR. There are some low cost resistor arrays available with 0.1% matching and low Tc that are great for this application that will allow for excellent CMRR without trimming. Use of low noise opamps and low impedances will also keep noise to a minimum. And, as mentioned in my previous post, broadband random noise (i.e., thermal noise) will average out to zero phase error given sufficiently slow PLL time constants.
Wouldn't manipulation of the phase detector in the PLL chip accomplish the same result?
Yes, I suppose it would, but how would you do that? I don't see how you could actually manipulate the edge sensitive PC2 in the 4046, particularly if not using the VCO as one of the PC inputs. The use of a monostable on one sense leg, as I mentioned, was just a quick thought with regard to nulling out any filter induced phase errors.
Regarding the 4046, does adjusting RV4 (OP schematic) provide some degree of phase trim? I had considered using the VCO output to feed an edge detector with those edges used to reset an integrator to provide the 2X sawtooth for the 494. Doing so would, however, require modifying/adjusting the integrator or current source for wide ranges of frequencies. As I said, your solution was rather unique. Tip of the hat to ya'...
I know the answer to this one:
That was just a proof of concept with the op-amp Itsu had on the breadboard. He knows well that the AD8032 is not suitable for driving high power loads. In a real application, such as the one you mentioned, the LC circuit would be driven by power MOSFETs driven by the PWM Controller (the TL494 in the first version of this circuit or a faster one in future versions).
Seeing how the Ruslan type threads began to decompose about the time people thought copper was being transmuted to steel based on a YT video, and have pretty much gone silent since, are there active threads on this forum where this continues to be pursued in private or closed to the public threads?
For example, the apparently limited access to the "New Developments" thread you linked to?
Just wondering...
PW
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Topic: Conventional (non-OU, but related) electronic circuit problem (Read 5649 times)
