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Author Topic: Long series MOSFETs for extreme HV switching?  (Read 198 times)

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Posts: 105
Came across this and was wondering if anyone has had any experience driving FET's in series?  (CASCODE/cascade)

Ideally we would want to drive each stage with a floating, galvanically isolated driver, but I think the incredible simplicity of the attached document makes it an option worth exploring. ???  I'll update this thread once I've done a few basic bench tests.


Step-recovery diodes and avalanching transistors look to be interesting options as well, but they tend to limit you to 1-2 kilovolts.  If we're going HV, may as well go full-bore.  And using spark-gaps tends to give you much less control.

(edit: added a PNG version of the document)
« Last Edit: 2019-02-06, 16:00:28 by Reiyuki »
   

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Posts: 150
Came across this and was wondering if anyone has had any experience driving FET's in series?  (CASCODE/cascade)

Ideally we would want to drive each stage with a floating, galvanically isolated driver, but I think the incredible simplicity of the attached document makes it an option worth exploring. ???  I'll update this thread once I've done a few basic bench tests.


Step-recovery diodes and avalanching transistors look to be interesting options as well, but they tend to limit you to 1-2 kilovolts.  If we're going HV, may as well go full-bore.  And using spark-gaps tends to give you much less control.


Well thats strange. Was just talking to Chet about this a couple days ago. I was wondering about how to use mosfets in series for higher voltage and looked it up. The info I had seen uses series resistors for voltage division with the gates at the between points of the resistor chain.

Was thinking of it because I want to use the Tesla igniter circuit to charge a cap to over a couple hundred volts for the SS nonsense and the SS orbos I have with very similar goals, but still have low Rds and such. Like for transistors Im working with, IRLB3034, 4 in series for example would give me 120v and .006ohm rds. The article said it also improved power handling. Ill post the info I has found when I get to my shop tomorrow night.

Mags
   
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Posts: 360
Hi Folks,

Just to widen the choices on HV switches with MOSFETs in series connection (cascade), here is a paper with the circuit on it:
http://bromine.cchem.berkeley.edu/grppub/frbm2.pdf   

The circuit is more involved than the really very simple yet most likely working solution Reiyuki referred to above.  Some of the older components shown from 1991 may already be superseded by now but the ideas can surely be implemented with todays components.

Gyula

edited for a typo
« Last Edit: 2019-02-06, 15:41:41 by gyula »
   

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Posts: 105
Another variation I've been seeing is similar to Gyula's, driving multiple pulse transformers with a single primary.
(You could probably use multiple toroidal pulse-transformers and run a single heavily-insulated wire through each one)

This method would probably be hard to tune to nanosecond switching speeds.
« Last Edit: 2019-02-07, 03:14:59 by Reiyuki »
   

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Posts: 105
Initial results with a 4-element cascode (1 driven element, the other three cascading) are promising (but ugly). C.C

The circuit 'works'.  With caps across the gates as described in the original post, the configuration causes the lower MOSFET to automatically trigger the rest in very rapid succession. 8)

Notes:  (Test performed with 1000pf caps, IRF840 MOSFETs and an extremely crude configuration.  20v drive to limit the possibility of gate damage).
* Total rise+fall time appears to be somewhat proportional to the number of FETs in series.  (10ns rise time for one FET means 40ns with 4 FETs.)
* Switch-off is about 2x the switch-on speed.  (Similar performance as driving a single MOSFET with the same driver)
* Without balancing, the topmost FET takes almost all of the shock. (EE's will see the same problem when using diodes in series)

Conclusion:  The concept appears to be viable, but good performance will require better snubbing and filtration circuitry.

* MOV's absolutely required across all gates with clamp voltage less than the limits of the FETs.
* MOV's likely required across source-drain as well, clamping voltage well below the source-drain limit.
* Additional source-drain resistance may be needed to balance the load between each FET.
* GDT's might prove useful both as bypass capacitance and for impulse shock absorption.
* The balance-capacitor values should to be greater than the gate capacitance of the FETs.
* The primary driver needs to be as fast and clean as possible.  Any oscillations on the low-end will ripple up through the chain. ;)

And of course, snubbers, bypass capacitors, schotkey diodes to help with harmonics and other interference (which is cumulative in circuits like this).  The test I performed used none of this, hence the somewhat horrific waveforms.


The next phase I think will be to design a proper PCB to help with all the artifacts encountered in this prototype, and to comfortably start testing higher voltages. :) :)


Came across this and was wondering if anyone has had any experience driving FET's in series?  (CASCODE/cascade)

Ideally we would want to drive each stage with a floating, galvanically isolated driver, but I think the incredible simplicity of the attached document makes it an option worth exploring. ???  I'll update this thread once I've done a few basic bench tests.

Step-recovery diodes and avalanching transistors look to be interesting options as well, but they tend to limit you to 1-2 kilovolts.  If we're going HV, may as well go full-bore.  And using spark-gaps tends to give you much less control.

(edit: added a PNG version of the document)
   

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Posts: 105
Follow-up on staged MOSFET driving experiment, https://www.overunityresearch.com/index.php?topic=3713.msg72107#msg72107

I built an 8-stage prototype board to test with; unfortunately it is not the simple drop-in solution I was hoping for. C.C

A few lessons learns from testing done so far:
- Triggering upper stages becomes cumulatively harder the more stages that are in-place.
- Resistances have to be balanced between low losses and fast triggering.  This changes with the voltage used, so a device build for 3kv input may not ripple-trigger below 1kv.
- The critical voltage to induce ripple-triggering also changes with the number of stages.  Each stage must have a sufficient gate displacement to trigger.
- The large mesh of stray inductance/capacitance makes the whole thing difficult to measure.


If I were to incorporate this concept in the future, I would limit to 2 or 3 stages max to keep everything stable, or use fully-isolated drivers in each FET stage.
   
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