Logic issue with hex-D F-F

[Grumpy]

I'm trying to use a SN74AHC174 Hex-D Flip-Flop as a ring counter.

CLR is tied "high" to V+ (might be part of my problem...)

Outputs 1 -5 go to a 5-input NOR gate.

When clock is OFF, NOR is high to input 1, so this looks good.

When clock is ON outputs 1 - 6 are sequential as they should be.

When I turn off the clock, a random output will be stuck HIGH.

Is this normal?

Should I turn off the logic circuit or is there some sort of clearing process to stop this from occuring?

I'm not very familiar with logic stuff...

[Grumpy]

Attached are some docs for the hex f-f and how to decipher the function table (truth table):

X means irrelevant
Q₀ means "level of Q before the indicated steady-state input conditions were established"

What does that actually mean?

Per the table when CLR is H, and CLK is L, Q output is whatever is was before?

In the TI Understanding Logic pdf it says:
In the input columns, if a row contains only the symbols H, L, or X, the indicated output is valid when the input configuration is achieved, regardless of the sequence in which it is achieved. The output persists as long as the input configuration is maintained.

So, guessing as I am, I think this means I need to pull CLR down (i.e. power off) when the clock is turned off.

[partzman]

Attached are some docs for the hex f-f and how to decipher the function table (truth table):

X means irrelevant
Q₀ means "level of Q before the indicated steady-state input conditions were established"

What does that actually mean?

Per the table when CLR is H, and CLK is L, Q output is whatever is was before?

Yes.  The Q output only changes to whatever the D line is prior to a clock rising edge.  The only exception of course is a clear [logic level 0] on the barClr input when Q then goes to a logic 0 state.

In the TI Understanding Logic pdf it says:
In the input columns, if a row contains only the symbols H, L, or X, the indicated output is valid when the input configuration is achieved, regardless of the sequence in which it is achieved. The output persists as long as the input configuration is maintained.

So, guessing as I am, I think this means I need to pull CLR down (i.e. power off) when the clock is turned off.

If you wish to "clear" the Q output or force it it a logic 0, it matters not what level or state the clock or data lines are in if the barClr line is taken to 0.  If the clock is say high after barClr is taken to a logic level 1, the clock must return to logic 0 and then on the next rising edge it will "clock" the existing logic level on the D line to the Q output.

Pm

[Grumpy]

Thanks Partzman!

I never took time to understand logic circuits.  I thought the clock controlled the output as well as the input, so no clock would mean no output.