NOR Gates

[Grumpy]

Is there any way to make a 5 input NOR gate with only a Quad 2-input NOR gate chip?

I have some of these: http://www.nteinc.com/specs/7400to7499/pdf/nte74128.pdf

I just hate to use another chip for one more input.

EDIT:

Nevermind...

I figured out how to do it.

[muDped]

Great logic problem!

So,  how'djaduit?

[Grumpy]

attached

[muDped]

Looks good!  Truth Table checks.

[Groundloop]

attached

Grumpy,

I did not get the truth table to check out OK on your circuit.
But I got the truth table right on the attached.

GL.

[Peterae]

Guys you cannot cascade NOR gates, you need to connect both inputs together to form a not gate after each 2 input nor to make an or gate and then feed that into the cascaded nor, It's a hard life this way for the cost just buy a 8 input nor LOL otherwise you will be using 2 chips instead of 1, and considering the cost of an 8 input nor it's not worth the trouble LOL

EDIT here's your easiest method just use 5 resistors on the input 

[Groundloop]

Guys you cannot cascade NOR gates, you need to connect both inputs together to form a not gate after each 2 input nor to make an or gate and then feed that into the cascaded nor, It's a hard life this way for the cost just buy a 8 input nor LOL otherwise you will be using 2 chips instead of 1, and considering the cost of an 8 input nor it's not worth the trouble LOL

EDIT here's your easiest method just use 5 resistors on the input 

Peter,

You can cascade any gates you want.
There is some restrictions with TTL as to number of inputs on one output.
The circuit I posted will work both with TTL logic and CMOS logic.

GL.

[Grumpy]

http://www.doctronics.co.uk/4001.htm

It requires an extra gate like Peter said.

I might have a 2N2222 around.

[Groundloop]

http://www.doctronics.co.uk/4001.htm

It requires an extra gate like Peter said.

I might have a 2N2222 around.

Grumpy,

No it does not! The circuit I posted will behave as a 5 input, one output NOR gate.
(But there is different pulse delay for the inputs to the output.)

GL.

[Peterae]

It's all about asking yourself the right question, the only time you want a logic 1 output on a 5 input NOR is when all inputs are logic 0

so if we now consider cascading NOR gates.

we take a 2 input NOR gate and feed both inputs logic zero we get a logic 1 out, but if you now cascade this logic 1 output into the input of the next NOR gate you have broken the zero input rule and will never get a logic 1 out again for all 5 inputs at 0.

So for every 2 input NOR gateS you need a NOT gate after to convert the NOR into an OR gate, so for 5 or 6 input NOR gate you would require.

6 gates for the first row giving 3 OR outputs, these then need to feed another 2 NOR gates with another 2 NOT gates (another 4 gate in total) giving 2 OR outputs which then feed the final NOR gate, that's a total of 11 gates required to meet the correct logic requirements.

[Groundloop]

It's all about asking yourself the right question, the only time you want a logic 1 output on a 5 input NOR is when all inputs are logic 0

so if we now consider cascading NOR gates.

we take a 2 input NOR gate and feed both inputs logic zero we get a logic 1 out, but if you now cascade this logic 1 output into the input of the next NOR gate you have broken the zero input rule and will never get a logic 1 out again for all 5 inputs at 0.

So for every 2 input NOR gateS you need a NOT gate after to convert the NOR into an OR gate, so for 5 or 6 input NOR gate you would require.

6 gates for the first row giving 3 OR outputs, these then need to feed another 2 NOR gates with another 2 NOT gates (another 4 gate in total) giving 2 OR outputs which then feed the final NOR gate, that's a total of 11 gates required to meet the correct logic requirements.

Peter,

5 input NOR define:

All 5 input LOW, output = HIGH.
One OR all of the inputs HIGH, output = LOW.

The circuit that I posted will work like that.

GL.

[Peterae]

Huh

One OR all of the inputs HIGH, output = LOW.

OR Gate Logic
00 = 0
01 = 1
10 = 1
11 = 1

One OR all of the inputs HIGH, output = HIGH



A NOR gate is all the inputs ORed and then NOTed thats why it's called a NOR Notted OR NOR

I suggest you look at your logic and your diagram

First try and it failed with a 1 on the output with 1 input high

NOR Gate logic
00 = 1
01 = 0
10 = 0
11 = 0

It is well known that NOTed gates cannot be cascaded

If a logic gate with a different number of inputs to the one available is required, one can be built up from the gates that are available. This is done by cascading the gates. Gates which are the "basic" gates (i.e. AND, OR, XOR) can be directly cascaded. The "negated gates" (NAND, NOR, XNOR) can't, and these are made up of the counterpart basic gate with an inverted output.

http://en.wikibooks.org/wiki/Practical_Electronics/Logic/Cascading#NOR

[Groundloop]

Peter,

Good morning. :-)

You are 100% right and I'm 100% wrong!

If we had used four OR ports and a inverter on the output, then it would have worked.
Or as you said, inverter between the ports.

GL.

[Peterae]

Merry Xmas Groundloop  

Logic was my best subject  

and yes it's normally me that is wrong so a nice change for me 

[Groundloop]

Merry Xmas Groundloop  

Logic was my best subject  

and yes it's normally me that is wrong so a nice change for me 

Peter,

Thank you and merry Christmas and a happy new year to you and your family.

Will the attached circuit work as a 5 input NOR?
(Not paying any attention to port delays.)

GL.

[Peterae]

Nice one Groundloop yes that's better than i suggested   and will work good

Happy New to you and your family also 

[Grumpy]

What are the rules for handling unused inputs and outputs? (in general)

[Peterae]

With NOR you want to pull any inputs low, early logic required a 1K resistor to pull high or Low 74XX, LS and ALS but newer logic can be tied without the resistor, i would always use a resistor myself and sometimes have a fish around to see what the manufacturer suggests, I'm not an expert with this as it's been years since i bothered with gates.

[muDped]

Aye, GroundLoop's circuit (a group of or'd OR gates)  as a
consequence of critically inserted inverters is a sound
solution.

Peterae's observation:

It is well known that NOTed gates cannot be cascaded

is so very true.

And I therefore am eating Crow for making a hasty
(and therefore wasteful) mental determination.
Truth Tables should always be done with paper and
pencil to avoid errors, particularly in advanced years
when minds are more like leaky buckets (ie. my bucket
has a hole in it.)

This discussion has become quite the learning experience!

What are the rules for handling unused inputs and outputs? (in general)

With CMOS logic it is most important to disable unused gates
on a chip to eliminate the possibility of noise pickup by "floating
inputs" which can affect the entire chip.    TTL logic chips aren't quite
as vulnerable so in many applications unused gates can be left
"floating" without troubles.

Unused gates can always be paralleled with used same gates to
assure that all gates are connected.

[Peterae]

Hi Dumped

Logic can take out the most clever people sometimes, i have seen it LOL

Truth Tables should always be done with paper and pencil to avoid errors

Absolutely, this is how groundloop worked the final solution and why his was better than my version, i never looked at it on paper.

[BEP]

With NOR you want to pull any inputs low, early logic required a 1K resistor to pull high or Low 74XX, LS and ALS but newer logic can be tied without the resistor, i would always use a resistor myself and sometimes have a fish around to see what the manufacturer suggests, I'm not an expert with this as it's been years since i bothered with gates.

I wish I could say the same 'years since'. You may understand my physiological problems if you new that I deal with them on a daily basis. 64, 65, 74, 75, (nothing), S, F, L, LS, A, H, HC, C and some of the most rare devices imaginable. We have stock on hundreds of different types that were custom made for specific OEMs. At some point somebody invented the PAL & GAL. We have those, too  

Some are so weird an impossible to cross that the manufacturer sleeved them in lead tubes.    

One would think that if we deal with such monstrosities that our engineers would know to pull unused gates but that isn't so. The two younger folks can't be convinced that a floating gate is a very bad idea ( I'll be firing them at first chance  ).

[Grumpy]

With NOR you want to pull any inputs low, early logic required a 1K resistor to pull high or Low 74XX, LS and ALS but newer logic can be tied without the resistor, i would always use a resistor myself and sometimes have a fish around to see what the manufacturer suggests, I'm not an expert with this as it's been years since i bothered with gates.

Based on this chip SN74F260 (attached)

If I am using only one side, do I ground the inputs for the other side, leave them open, tie them together, or

If I am using 3 of the 5 inputs, what do I do with the other 2?

Thanks to everyone!

[Groundloop]

Based on this chip SN74F260 (attached)

If I am using only one side, do I ground the inputs for the other side, leave them open, tie them together, or

If I am using 3 of the 5 inputs, what do I do with the other 2?

Thanks to everyone!

Hi Grumpy,

First, I'm sorry to clutter your thread with my mistakes. But thanks to Peter we got it right. My dinner today was Boiled Crowbar! :-)

Is it possible for you to post your circuit drawing or parts of it? It is much more easy to look at a design drawing.

But, in general, on your NOR port you can ground (tie to Vss) the unused INPUT ports. You leave
the output port open, if unused. So if you want to use the 1A to 1E as inputs, the 1Y as output,
and only 3 of the 5 inputs on 2A to 2E, then you just ground the 2 unused ports to ground (tie to Vss).
The 2Y will be your second output. As I understand it, you need one NOR with 5 inputs, and one NOR with three inputs?

GL.

[Grumpy]

The 5 input NOR is for a hex D flip flop ring counter, to ensure that it always starts.

The 3 input NOR is just so that I know for future use.  A tetrahedral device only needs a 2 input NOR, which I already have.

[Groundloop]

The 5 input NOR is for a hex D flip flop ring counter, to ensure that it always starts.

The 3 input NOR is just so that I know for future use.  A tetrahedral device only needs a 2 input NOR, which I already have.

Grumpy,

OK, I think I understand. When you design your circuit you just ground the two unused ports on
the second NOR in the IC. The three future ports must not be left open if not used right now.
I assume those three ports will go somewhere in a future version? So you just design into you
printed circuit board some jumpers that you ground (tie to Vss) for now. Later on you just remove
those jumpers. You can also design some plugged jumpers for that purpose. You know the small
plugs that goes into the back of hard drives? They have a pin pitch of 2,54mm. So in your PCB
design you can use pins for that purpose. In the future you just remove the plugs to un-ground
your three inputs.

GL.