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Author Topic: partzmans board ATL  (Read 36254 times)
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Re: partzmans board ATL « Reply #500 on: 2024-10-17, 15:48:06 »
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This is yet another attempt to show proof of dielectric induction or charge separation in a capacitor when placed in an E-Field.

The first pix is the layout used.  I was hoping that the direction arrow on the current probe would show but unfortunately it does not.  It is pointing towards Ct.  CH3(pnk) is connected at the top of the Ct and white wire junction and both the CH3 and current probe grounds are connected at the bottom of the Ct and white wire junction.

The ST9 Layout Schematic shows the electrical schematic for the circuit.  IOW, the single turn white wire and Ct are in parallel and both subjected to the majority of the E-Field in the toroid core.  The V/t in this case is 3.2v/turn.

The ST9 SP1 scope pix shows the results.  Here we clearly see that the voltage across Ct and the white wire reaches 3.005v in 200ns.  We also see that the conventional current flow is negative into Ct thus meaning that the current flow is positive out of Ct and into the white wire!  IMO, this is due to the difference between the series inductance of Ct and the inductance of the white wire with the latter being greater.  With the CH3 scope probe removed, this current does not change!

Regards,
Pm 
   
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Re: partzmans board ATL « Reply #501 on: 2024-10-18, 07:15:33 »
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Thanks Jon,

This process does align with Mikes designs in one important way.
Also lester hendershot.

Over the next few weeks I will try axial wound caps inside torriods ,of which I have many .

Electrolytics may need the cans removed ...nasty stuff! gloves required.

Others might do some as well .

In my case it will be just to obtain charge and hopefully move on from there.
In light of Mikes work a bias voltage may assist, but pure speculation on my part.

A diy cap of thin copper sheets seems worth a go as well .
« Last Edit: 2024-10-18, 08:22:21 by 3D Magnetics »
   
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Re: partzmans board ATL « Reply #502 on: 2024-10-18, 09:16:29 »

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Pm,

Not surprisingly I have a different take on your results.  I don't see the 3V induction as being Ct charged to 3V.  But what I do see is your current settling down to about 8mA smooth, then falling away.  IMO that 8mA is charging Ct and that means it is gaining voltage (and charge and energy) at a rate of 8uA per nS.  If you follow the waveform for a longer period of time that 8mA will probably drop to zero, then the integral of that current up to that zero point will tell you the voltage gained by Ct (and also the energy gained by Ct).  Where has that energy come from?  That could be your dielectric induction effect.  The closed loop of white wire in parallel with Ct should not theoretically induce voltage into Ct as it does not enclose the core flux.  Is there some way you could reclaim that small energy?  Just my twopenny-worth of input.

Smudge   
   
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Re: partzmans board ATL « Reply #503 on: 2024-10-18, 16:43:30 »
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Quote from: 3D Magnetics on 2024-10-18, 07:15:33
Thanks Jon,

This process does align with Mikes designs in one important way.
Also lester hendershot.

Over the next few weeks I will try axial wound caps inside torriods ,of which I have many .

Electrolytics may need the cans removed ...nasty stuff! gloves required.

Others might do some as well .

In my case it will be just to obtain charge and hopefully move on from there.
In light of Mikes work a bias voltage may assist, but pure speculation on my part.

A diy cap of thin copper sheets seems worth a go as well .

3D,

Yes, I have seen the possibility of the TPU utilizing this concept in the form that Mike has presented.

Bias voltages added to the Ct adds to the apparent energy levels but the basic problem remains and that is, as the Ct tracks the primary voltage, any increases are met with decreases as the primary voltage changes.

Regards,
Pm
   
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Re: partzmans board ATL « Reply #504 on: 2024-10-18, 17:22:54 »
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Quote from: Smudge on 2024-10-18, 09:16:29
Pm,

Not surprisingly I have a different take on your results.  I don't see the 3V induction as being Ct charged to 3V.  But what I do see is your current settling down to about 8mA smooth, then falling away.  IMO that 8mA is charging Ct and that means it is gaining voltage (and charge and energy) at a rate of 8uA per nS.  If you follow the waveform for a longer period of time that 8mA will probably drop to zero, then the integral of that current up to that zero point will tell you the voltage gained by Ct (and also the energy gained by Ct).  Where has that energy come from?  That could be your dielectric induction effect.  The closed loop of white wire in parallel with Ct should not theoretically induce voltage into Ct as it does not enclose the core flux.  Is there some way you could reclaim that small energy?  Just my twopenny-worth of input.

Smudge

Smudge,

With the scope horizontal deflection lowered to 1us/div, we see what is actually happening with the current.  It is resonating at 425.5kHz as seen in SP3 below.  Analyzing this, we conclude that the network inductance is Lz=1/w^2*Ct=127nH including all lead inductance plus Ct's serial inductance.  Essentially then IMO, it is parallel resonant network that has been simultaneously charge separated.  As I stated in my previous post, there is a differential in inductance between where the probes are attached physically that provides the slight current differential which is the source for exciting the small level of resonance.

Close examination of SP2 reveals IMO the fast rise of current at the start of oscillation which I have demonstrated previously that happens during the initial startup of a parallel resonant network.  The average current then falls to equal zero after successive cycles.

I do not agree that these small currents are responsible for the charging of Ct but rather again, Ct is charge separated by the E-Field and the resultant energy or charge contained within Ct, is supplied by the aether.

Regards,
Pm

   
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Re: partzmans board ATL « Reply #505 on: 2024-10-19, 16:18:27 »
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3D and all,

Well, the following came as quite a surprise as I did not expect to see these results!  I had not thought of trying electrolytics for whatever reason but when 3D mentioned trying them and removing the outer aluminum case, I gave it a try.  I reasoned that possibly the case would not need to be removed and that turned out to be correct for either axial or radial 'lytics!!

So, this test uses a 2500uf-25v axial 'lytic C1 positioned as shown in the Layout pix below.  As previous, the V/t is 3.2 and the positive terminal of C1 is connected through a parallel combo of a 1.2k resistor R1 and a Schottky diode D1 to a 15v DC Vload supply.

SP1 shows the resulting current drive from C1 to Vload which results in a returned energy of PLoad=11.97W over 17.35us resulting in a Uload=11.97*17.35e-6=207.7uJ .

SP2 and SP3 show the starting and ending voltages across C1 of 14.92v and 14.95v respectively over the cycle.  In theory, this represents an energy gain in C1 of UC1=(14.95^2-14.92^2)*2500e-6/2=1.12mJ .

SP4 shows the Pin of the primary to be 13.93W over 17.43us for a Uin=13.93*17.34e-6=241.5uJ .

SP5 shows the returned power to the 64v DC supply form the collapsing primary current to be 8.938W over 16.25us for a Uret=145.2uJ .  This results in a net input energy consumption of (241.5e-6)-(145.2e-6)=96.3uJ .

Comparing this to the Uload=207.7uJ in SP1, this results in an apparent COP=207.7/96.3=2.16 .  This does not take into account the apparent gain of 1.12mJ in C1!

SP6 is a check of the influence of R1 on the voltage increase in C1 when the primary voltage has reversed causing C1 to be 3.224v more negative than Vload over ~16.4us.  The average current during this time would be 3.224/1200=2.7ma .  Since dV=di*dt/C, we can calculate that dV=(2.7e-3*16.4e-6)/2500e-6=17.7uV.  Therefore, we can see that R1 does not materially affect the voltage rise in C1 so we have to assume that the ending voltage voltage across C1 is reasonably accurate.

IMO, this test raises a lot of questions!

Regards,
Pm

Edit: Please note that the primary current in SP6 clearly indicates saturation in the core.  With a larger core area, the efficiency or COP would greatly improve! 
   
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Re: partzmans board ATL « Reply #506 on: 2024-10-19, 17:58:45 »

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I think what you have created is a small "magnetic loop", if you google that it will explain more than I can write here.

It is the cause of the anomally which SM came across to create the TPU, it is also what I use in STEAP to create a large current in the core (copper) which then creates an external magnetic field.

In your case you are using a ferrite toroid with some turns on it connected to your signal source, and then placing the capacitor, and wire, through the toroid to an external capacitor.

It is that external capacitor along with the inductance of the wire, and internal capacitor, that creates the magnetic loop. The max voltage should be at the external capacitor, being that both capacitors are +- 180º to one another, both voltages would be the same.

If you remove the cap inside the toroid and join the ends of the two wires together so as you only have the external cap at 180º to the toroid, you should still see the voltage on that external cap. The voltage maybe double what you have seen before, the current will be highest in the connecting wire "loop", and why it is called a magnetic loop, the near field is magnetic, and can act like a ferromagnetic core which has NO loss.

As a radio HAM I realised what was happening, of which I tried some years ago, 2021, to get people to realise whith the aluminium loop and high circulating currents. Circulating currents as we ALL know, create a magnetic field. The circulating current is more or less uniform in the loop, but the high voltage is at the capacitor and moving down to near zero @ 180º to the capacitor.

PM me if you want to discuse this further, you are on the right track but not realised the significance.

Regards as always for your work

Mike



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Re: partzmans board ATL « Reply #507 on: 2024-10-19, 21:54:18 »
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This is the schematic used in post #505 for those interested in replicating.

To measure the power put into Vload, CH3(pnk) is placed on Vload and the current is measured on line VC1.

CH3(pnk) is placed on VC1 to measure the start and finish voltages on C1.

My 2500uf lytic was rated for 25v DC max so I could have used 25-V/t or 25-3.2=21.8 safely for Vload.  Using this voltage on Vload yielded Uload=-276uJ with a net Uinet=95.2uJ for a COP = 2.99 .  This again is ignoring the the energy gain in C1.

Regards,
Pm
   
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Re: partzmans board ATL « Reply #508 on: 2024-10-19, 22:02:10 »
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Quote from: Centraflow on 2024-10-19, 17:58:45
PM

I think what you have created is a small "magnetic loop", if you google that it will explain more than I can write here.

It is the cause of the anomally which SM came across to create the TPU, it is also what I use in STEAP to create a large current in the core (copper) which then creates an external magnetic field.

In your case you are using a ferrite toroid with some turns on it connected to your signal source, and then placing the capacitor, and wire, through the toroid to an external capacitor.

It is that external capacitor along with the inductance of the wire, and internal capacitor, that creates the magnetic loop. The max voltage should be at the external capacitor, being that both capacitors are +- 180º to one another, both voltages would be the same.

If you remove the cap inside the toroid and join the ends of the two wires together so as you only have the external cap at 180º to the toroid, you should still see the voltage on that external cap. The voltage maybe double what you have seen before, the current will be highest in the connecting wire "loop", and why it is called a magnetic loop, the near field is magnetic, and can act like a ferromagnetic core which has NO loss.

As a radio HAM I realised what was happening, of which I tried some years ago, 2021, to get people to realise whith the aluminium loop and high circulating currents. Circulating currents as we ALL know, create a magnetic field. The circulating current is more or less uniform in the loop, but the high voltage is at the capacitor and moving down to near zero @ 180º to the capacitor.

PM me if you want to discuse this further, you are on the right track but not realised the significance.

Regards as always for your work

Mike

I'll have to study what you've written above because in this circuit, the current you see measured as 696.1ma mean is the only current in C1 for the cycle.  It is actually driving the output capacitance in the Tek PS5010 power supply which at this time I don't know the actual value.

If I place a wire in the core replacing C1, the voltage across it will be exactly the same as across C1.  However, I will not be able to bias the wire with Vload because it will appear as a short as you well know.

Still , I will reflect more on what you've stated to see if I come to an understanding!

Regards,
Pm 
   
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Re: partzmans board ATL « Reply #509 on: 2024-10-20, 02:50:50 »
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Interesting!

I am now winding a 3 plate capacitor from the guts of a LITIC cap with no electrolyte. I want to apply fully isolated  bias to encourage plasma.

I have 3 primary windings to experiment with 3 frequencies ,all from separate and 2kv isolated dc supplies, forcing any interaction into near field magnetic only. 

Mike,
I would like your take on this.

Could it be that the center torroids were the main thing?
early days ,much to test yet, but my mosfets are safe here ..I ASSume
   
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Re: partzmans board ATL « Reply #510 on: 2024-10-20, 08:34:25 »

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At rf it is not a short, it is a resonant circuit, LCR.

Look up small magnetic loop antenna.

Regards

Mike


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Re: partzmans board ATL « Reply #511 on: 2024-10-20, 11:13:18 »

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From my phone, but you shoukd get the idea.

You maybe inputing a few khz but the resonance is in the mhz.

Note in fig 3 things are reversed.

There are many options to this, the capacitance in the loop could be just a gap!! and not an actual component.

Regards

Mike


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Re: partzmans board ATL « Reply #512 on: 2024-10-20, 16:19:11 »
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This is a follow up of my posts #505 and #507 using 'Lytics however, this test was run with 2 stacked toroids to increase the primary inductance and reduce some saturation.

The Layout below shows the configuration used.  primary is still 20 turns and the primary pulse is still 64v supplied via a 3/4 bridge.

SP1 shows the Pin to the primary equals 9.328W over 17.45us for a Uin=9.328*17.45e-6=162.8uJ . 

SP2 shows the returned power to the 64v DC supply to be 5.908W over 16.95us for a Uret=5.908*16.95e-6=100uJ .  This results in a net Uinet=62.8uJ .  Note there is still an amount of saturation in the primary.

SP3 shows the power delivered to Vload to be 18.02W over 17.37us for a UVload=18.02*17.37e-6=313uJ .  This is an apparent COP=313/62.8=4.98 .  Note that the voltage level of Vload in this case was increased to 21.8v to allow a slight safety margin for the increase in voltage across C1 no to exceed 25v.

To utilize this gain in a continuously running circuit, a load must be presented across Vload to keep the average voltage across Vload at ~21.8v for this example.  If the  load is removed, Vload will pump up until there is no difference between it and the voltage across C1.  In this case, the output ceases but Uinet will continue on so the cycles then must simply cease until a load is attached. 

SP4 and SP5 show the starting and ending voltage levels across C1.

Regards,
Pm
   
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Re: partzmans board ATL « Reply #513 on: 2024-10-21, 19:41:55 »

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Quote from: 3D Magnetics on 2024-10-20, 02:50:50
Interesting!

I am now winding a 3 plate capacitor from the guts of a LITIC cap with no electrolyte. I want to apply fully isolated  bias to encourage plasma.

I have 3 primary windings to experiment with 3 frequencies ,all from separate and 2kv isolated dc supplies, forcing any interaction into near field magnetic only. 

Mike,
I would like your take on this.

Could it be that the center torroids were the main thing?
early days ,much to test yet, but my mosfets are safe here ..I ASSume
Not really been following this but why not a triode valve, or a vacuum capacitor in the center instead of a cap, probably need to make one with the correct config of the plates
   
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Re: partzmans board ATL « Reply #514 on: 2024-10-21, 19:55:22 »

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Yeah, a good cap will hold a charge for a long time.  Enough to be taken out of circuit and measured with HighZ TE.
   
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Re: partzmans board ATL « Reply #515 on: 2024-10-22, 08:14:54 »

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When you measure the induced voltage from a single wire passing through the core hole the induction effect (E field from -dA/dt) pumps charge from one end of the wire around the outside circuit and back into the other end of the wire.  The quantity of charge needed to get PM's Vout depends of course on whatever the outside return circuit is.  If just a scope probe measuring open circuit output that quantity is very small, just eneough to charge the stray capacitance across the output terminals plus scope probe capacitance.  If the piece of wire is replaced by a high value capacitor then the quantity of charge remains much the same.  It is that same small quantity of charge that is pumped out of one end of the capacitor and into the other end.  If the capacitor starts with zero charge, it gains that small quantity in that initial transaction.  The capacitor does not magically gain the open citcuit voltage as charge, induced voltage is not charged voltage.  In this new experiment the capacitor is initially charged up to the load battery voltage.  Now a quantity of charge is pumped around the circuit, and that pumps energy into the battery that is correctly determined by Pm's  measurements and calculations.  But in that process the capacitor loses charge, that pumped quantity is  charge loss.  When that is correctly taken into account there is no OU here.  Pm will disagree with this (as he has every right to do) but I feel people interested in following this should know my take on it.  All the data is there to do the calculations correctly.

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Re: partzmans board ATL « Reply #516 on: 2024-10-22, 15:14:26 »
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Smudge and all,

I was curious as to why with an electrolytic in the circuit in my post #512 settled to a voltage slightly higher than the start voltage after producing energy in a Vload when all film caps lost energy under the same conditions.  As it turns out, all is not as it it appears!

So, here is my latest observation of the cap used in post #512 which measured 2760uF .  The idea of this test was to see what the actual capacitance of C1 is under the influence of dielectric induction or charge separation.  The results were quite surprising!!

Lytic3 Schematic shows the circuitry measured in the following scope pix.  The V/t is 3.2v as used in the post #512 test, but there is no bias voltage on C1.  A 48uH inductive load L2 is used to discharge C1 for a measurement of the capacitance of C1.  The current in L2 is kept linear for an accurate a measurement as possible.

SP1 shows the basic waveforms seen, but here we focus on the average voltage on C1 of 3.12v that is measured with the CH3(pnk) cursors near the start of the discharge cycle.

SP2 then shows us the average voltage on C1 to be 2.98v near the end of the discharge cycle again measured with the CH3 cursors.

SP3 then shows us the mean current in L2 to be 1.007A over 31.36us via the CH4 cursors plus, a peak current reached in L2 of 1.982A .

Using these numbers we'll first solve for the charge separated capacitance.  Since dV=di*dt/C, C=di*dt/dv .  So, dV=3.12-2.98=.14v .  So, C=(1.007*31.36e-6)/.14=225.5uF .

Next we'll calculate the energy in L2 at 31.34us when the peak current has reached 1.982A .  Ul2=1.982^2*48e-6/2=94.3uJ .

Finally we see what energy was lost in C1 to charge L2.  UC1=(3.12^2-2.98^2)*225.5e-6/2=96.3uJ .  These two energies are close enough to assume the value of C1 to be reasonably accurate.

So what does this mean?  We observe C1 with a measured capacitance of 2760uF having a charge separated capacitance of 225.5uF !  Is this due to the shielding effect of the aluminum housing?

To me the most important question is, how these results relate to the test in post #512?  According to this test, we should have 225.5uF being charge separated on top of the nominal 2760uF.  Is this correct?  If so, does this interaction of capacitance and charge somehow allow for the apparent zero cycle loss in C1?

Regards,
Pm 

Edit:  I have tested many other 'Lytics and the results vary but are the results are similar to the above.  Even tantalum caps exhibit this characteristic but with a higher DI value.
   
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Re: partzmans board ATL « Reply #517 on: 2024-10-23, 15:14:47 »
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Regarding the test above, it would appear preliminarily from additional testing that the amount of charge separated capacitance is dependent on S=EXH or the power flow for any given set of core conditions.

This gets more interesting by the minute!

Regards,
Pm
   
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Re: partzmans board ATL « Reply #518 on: 2024-10-23, 16:35:31 »
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Quote from: partzman on 2024-10-23, 15:14:47
Regarding the test above, it would appear preliminarily from additional testing that the amount of charge separated capacitance is dependent on S=EXH or the power flow for any given set of core conditions.

This gets more interesting by the minute!

Regards,
Pm

This does not appear to be the case!  It is far more complicated IMO and appears to be above my pay grade!!

Regards,
Pm

Edit: I have found that my tests were affected by core saturation so it is not really that complicated.  There still may be a relationship to S=EXH.
   
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Re: partzmans board ATL « Reply #519 on: 2024-10-23, 21:45:39 »
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This is a demo of a 7 cycle burst of the circuit shown in the schematic below that is a follow up on my post #512 

This example is OU and can be extended for more cycles however, with the 100 ohm load, the energy supplied to Vload will eventually increase the voltage on Vload after X number of cycles to a point where the dV on C1 will not have enough potential to force D2 to conduct.  At this point, the input energy is wasted as no output energy will be developed.  So, Vload must be discharged back to the starting level and repeat.  In a final product utilizing this technology, a processor would supply the necessary timing and duty cycles to allow continuous operation with varying loads.

The schematic shows the values used.  Note the changes in V1 and the primary turns.  This all still results in a V/t=3.2v .  The M1 mosfet switches in the 100 ohm, 1%, non-inductive load resistor at the beginning of the entire cycle and disconnects the resistor after ~217us.

SP1 shows both the current on CH4(grn) and voltage on CH3(pnk) for the Vload line with the conventional current flowing into Vload.  The Math(red) channel shows the mean power to be 1.946W over 223.4us resulting in an energy level UVload=1.946*223.4e-6=435uJ .  Note the negative power levels during the time C1 is following the negative dV on the primary.  During this time, R2 is drawing power from Vload creating the reverse current flow.

Sp2 shows the mean current in R2 in CH4 of 220.3ma over 223.4us.  This equates to an energy level of UR2=.2203^2*100*223.4e-6=1.084mJ .

SP3 shows the Pin on the Math channel to the primary including the less than optimum 3/4 bridge drive circuitry to be 1.593W over 231.8us .  This equates to a Uin=1.593*231.8e-6=360uJ .

Therefore, we see a COP=(435+1084)/360=4.11 .

SP4 simply shows the starting and ending voltages on C1 measured at VC1 with CH3 to be essentially the same.  This is requiring more study to completely understand as far as I'm concerned.

There is only one source for this excess power IMO and that is the aether during each charge separation or dielectric induction event of C1.  I am more than happy to hear other explanations or to hear of any missed calculations, etc.

Regards,
Pm

 
   
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Re: partzmans board ATL « Reply #520 on: 2024-10-24, 01:21:32 »
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Excellent post PM !!

This has been a sticking point for a long time (the center torroid)

It may be that a passive device could be created .
It may also be that "its just the way the coils (and capacitors ) interact with each other"

Thank you for your hard work ,Smudge as well as the devils advocate is always useful and will continue to be so .

Why something should not work is vital to us all.


Another thought.

there is more to capture and in the first tpu there is possibly 2 disks of foil upper and lower which could capture the outer field which is exposed to more of the "environment".
Just a brain storm at this stage .
A wikapedia picture.
« Last Edit: 2024-10-24, 03:27:44 by 3D Magnetics »
   
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Re: partzmans board ATL « Reply #521 on: 2024-10-24, 21:11:23 »

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Looking at the COP results Partzman is showing, although not fully understanding how these results came about, i decided to start a replication in the hope the understanding will come underway.

 
I bread boarded the 3/4 Bridge drive circuit using some components available here, like an IRFP9240 P-channel MOSFET and 2x IRFP260N N-channel MOSFETs following the diagram from post #507 in the thread and with the help from Partzman.
I used 2x IXDD614PI MOSFET drivers driving the N-channel MOSFETs.

I use a battery operated FG as input signal (DC square wave 30kHz around 50% duty cycle) as to not run into ground loop problems when using the (grounded) scope probes later on.
I use 12V (minus isolated from ground) on the MOSFET drivers and CD4049 and 40V (also minus ground isolated) on the P-channel source (the zener in the P-channel MOSFET gate is 12V).

i did not succeed in finding the correct core for L1 (2.5mH with 20 turns) so i had to increase the number of turns to about 150 to get this 2.5mH inductance.

The resulting voltage across this L1 is not the 10V DC square wave seen in PM his screenshots (yellow), but an AC square wave doubling the 40V input voltage.
So i made a LTspice simulation of this circuit i have USING RANDOM AVAILABLE P- AND N-CHANNEL MOSFETS FROM THE LIBRARY, see here:



This simulation confirms the AC square wave i see when using a 2.7mH inductor as L1.

The simulation is attached below.

When i get the same DC square wave signal on L1 as shown by PM i will be able to continue building the Vload circuit and start making measurements from there.

Here the voltage across (yellow) and the current through (green) L1 on my bread boarded circuit:



Regards Itsu
« Last Edit: 2024-10-25, 15:54:52 by Itsu »
   
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Re: partzmans board ATL « Reply #522 on: 2024-10-25, 17:05:02 »

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I found and now use a Finemet core FT-3K50TS with an OD = 63mm and AL=27.1uH/N2 at 100kHz with 14turns measuring 8.7mH
   
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Re: partzmans board ATL « Reply #523 on: 2024-10-25, 20:24:13 »
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Quote from: Itsu on 2024-10-25, 17:05:02
I found and now use a Finemet core FT-3K50TS with an OD = 63mm and AL=27.1uH/N2 at 100kHz with 14turns measuring 8.7mH

Itsu,

That should work well to supply relatively large V/t.  Just watch out for core saturation because Ct will react like a regular secondary in the fact that the voltage across Ct will begin to drop at the onset of saturation.

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Pm
   
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Re: partzmans board ATL « Reply #524 on: 2024-10-25, 21:26:13 »

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Jon,

OK,  thanks.

Now, concerning the voltage across L1 using the 3/4 Bridge.

I now drive the circuit using my Rigol FG in burst mode (1 pulse per 100ms).
As the Rigol has a grounded lead, i cannot directly measure the voltage across L1 using a single probe as its ground lead will short out the MOSFET, so i use 2 probes in differential mode and subtract the result using the math function.

Here is my result of the voltage across L1 (40V supply on the MOSFET) in red and the current through L1 in green.



So i have an AC square wave across L1 (+/- 40V).
The current trace shows saturation where the green trace curls up.

Can you confirm that you also have such an AC square wave voltage signal across L1?

Itsu
   
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