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Author Topic: partzmans board ATL  (Read 36189 times)

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I checked the 1N5819's and both are OK, the 1.2K resistor measures 1.194K so is OK also.

Itsu
   
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I checked the 1N5819's and both are OK, the 1.2K resistor measures 1.194K so is OK also.

Itsu

OK, how about the possibility of R2 being inductive?

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Well, its a induction free 1% 100 Ohm resistor which are known for their low induction.
« Last Edit: 2024-11-03, 21:25:12 by Itsu »
   
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Well, its a induction free 1% 100 Ohm resistor which are known for their low induction.

OK, not knowing anything about what you are using for V2, try placing a 100-500uf or larger electrolytic cap across V2.  For some reason V2 does not appear that it has sufficient output capacitance to hold the voltage relatively constant at Vload.

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V2 is a DC PS 0-15.5V / 40A (Manson SPS9400), so should have enough output capacitance IMO.

The problem is that i have no understanding in what you are trying to do with this Vload circuit and how it supposes to work.

Perhaps you can (again?) explain in some detail what your goal is with this circuit, so i could try to find the problem in it.


I measure 153mA average through R2 during the 250us on time (every 100ms) when M1 switches to ground which is as expected for a 100 Ohm resistor at 15.5V.
I measure 317mA average right behind D2 coming from C1 (7 pulses) during that same on time every 100ms.

Itsu
   
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V2 is a DC PS 0-15.5V / 40A (Manson SPS9400), so should have enough output capacitance IMO.

The problem is that i have no understanding in what you are trying to do with this Vload circuit and how it supposes to work.

Perhaps you can (again?) explain in some detail what your goal is with this circuit, so i could try to find the problem in it.


I measure 153mA average through R2 during the 250us on time (every 100ms) when M1 switches to ground which is as expected for a 100 Ohm resistor at 15.5V.
I measure 317mA average right behind D2 coming from C1 (7 pulses) during that same on time every 100ms.

Itsu

OK, it is my mistake to assume that everyone understands the circuit operation!  I will reference the circuit used in my post #519 and have listed both the schematic, SP1, and SP4 below.

Now, look at the SP1 scope shot.  First, before we start the seven pulse sequence, we have the potential at Vc1 of 21.55v that is equal to the potential at Vload due to R1. 

At the first positive pulse from our SG to the 3/4 bridge, we create a positive voltage on VL1 while VL1a is ~ 0v.  This immediately creates a positive voltage rise on C1 via charge separation that is ~1 V/t (~3.2v in this case) above Vload minus the voltage drop across D2.  This voltage increase across C1 creates the half sine looking current seen on CH4(grn) that is flowing into Vload.  CH3(pnk) connected to Vload shows the  resulting increase in Vload during the time the SG pulse is positive.

Then, when our SG pulse goes to 0v, VL1 now goes to ~0v and VL1a goes positive.  This immediately creates a negative voltage drop on C1 that is again ~1V/t or ~-3.2v.  We don't see this negative voltage drop on C1 at this time because CH3 is connected Vload which has enough internal capacitance to hold Vload relatively constant as D2 decouples the negative drop on C1 from Vload.  However, we do have R2 connected to Vload during this time and it's loading creates the negative going voltage ramp we see on CH3 during the time the SG pulse is 0v.

SP4 gives us a view of the alternating voltage changes on C1 with CH3 connected to Vc1.

So, during this first complete cycle, we have supplied energy to the Vload supply and to our load resistor R2.  This is our goal.

This same action repeats over the next 6 cycles. 

The reason that the current in CH4 is seen to go negative during the time C1 is decoupled from Vload is because Vload is supplying energy to R2 during this time in the cycle.  During the rest of the cycle, C1 is supplying energy both to Vload and R2.

I hope this makes sense and helps.

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thanks for doing this, i will study this to see where i go wrong.

One thing i have now a problem with is when you say:

Quote
This immediately creates a positive voltage rise on C1 via charge separation that is ~1 V/t (~3.2v in this case) above Vload minus the voltage drop across D2.

Looking at the below modified SP1 screenshot, i see that the pink trace vertical setting is set at 3.24V/div, and the increase of the pink trace is 1.903V while you mention: (~3.2v in this case) above Vload minus the voltage drop across D2.

Voltage drop of D2 is ~0.2V, so according to that we should have an increase of ~3V, but the screenshot shows the 1.903V increase only.

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thanks for doing this, i will study this to see where i go wrong.

One thing i have now a problem with is when you say:

Looking at the below modified SP1 screenshot, i see that the pink trace vertical setting is set at 3.24V/div, and the increase of the pink trace is 1.903V while you mention: (~3.2v in this case) above Vload minus the voltage drop across D2.

Voltage drop of D2 is ~0.2V, so according to that we should have an increase of ~3V, but the screenshot shows the 1.903V increase only.

Itsu

Itsu,

In SP1, C1 is loaded with the current feeding Vload and therefore does not reach the ~3.2v peak voltage level although one can see it is increasing in voltage as the first pulse progresses.

Take a look at SP4 in my post #555 above and you will see the open circuit voltage reached in C1 is ~3.2v.

I will also point out that this event is not Lenz free!  Once C1 is charge separated in the first 50-200ns, whatever happens to C1 is then reflected back to the primary.

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thanks for the info.

Still studying the circuit.

What i in the meantime did was adding capacitance (10000uF) to the 15.5V PS (Vload), but it did not change the shape of the current (no half sine wave) nor the shape of the Vload voltage.

I then changed the PS's so i now have the same voltages as you have, meaning 12V on the 4049 / IXDD614PI driver, 48V on the MOSFETs and 21.8V as Vload.

So i now have 48V / 8 turns =  6V/Turn.

But also this did not change the shape of the traces as can be seen below.


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thanks for the info.

Still studying the circuit.

What i in the meantime did was adding capacitance (10000uF) to the 15.5V PS (Vload), but it did not change the shape of the current (no half sine wave) nor the shape of the Vload voltage.

I then changed the PS's so i now have the same voltages as you have, meaning 12V on the 4049 / IXDD614PI driver, 48V on the MOSFETs and 21.8V as Vload.

So i now have 48V / 8 turns =  6V/Turn.

But also this did not change the shape of the traces as can be seen below.


Itsu

Itsu,

Something is definitely wrong somewhere in your output circuit! 

I've attached a partial schematic of just the output circuitry below.  With the CH3 and CH4 connections as shown, when Vc1 goes more negative than Vload during the second half of each pulse cycle, D2 decouples Vc1 from Vload with only a slight loading from R1 which we ignore.  During this time, CSply attempts to hold Vload at a constant voltage.  However, we have R2 connected across Vload which presents a near constant current load to Vload which will result in a near linear voltage decrease in Vload depending on the value of CSply.  My circuit exhibits this action but yours does not!

One thing to note.  I do not use a 1N5819 but rather an STPS2150 Schottky rated at 150v, 2 amps.  This should not really matter as the reverse capacitances are relatively close and the voltage levels are not high enough to break down the 1N5819 into reverse conduction.

Regards,
Pm
   

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PM,

I do had the same circuit and probe positions, but now i changed the C1 circuit from a breadboard to a soldered proto board.

Now the CH3 pink trace shows a different shape, more like yours, see screenshot.
The green current trace does not resemble your half-wave sine shape yet.

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I do had the same circuit and probe positions, but now i changed the C1 circuit from a breadboard to a soldered proto board.

Now the CH3 pink trace shows a different shape, more like yours, see screenshot.
The green current trace does not resemble your half-wave sine shape yet.

Itsu

OK, I didn't realize you were using a breadboard!  Yes, your wavefroms are getting closer now but I would still say that you have more inductance in your connecting leads than I have which is making the current resonance shape a lower frequency.

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Ok, so there is resonance involved, is that needed?

I shortened the leads from C1 to R1 / D2 from 10 to 5cm and reduced the leads from my 21.8V PS (Vload) from 50 to 15cm.

There is some change, but only a little, see screenshot.

What components are involved for this inductance to get resonance?


After many experiments, it seems almost impossible to get the same traces, as all toroids and number of turns on them i used up till now all show a different outcome in trace shape.
It would be best to know the exact used toroid, the number of turns used and the makeup of the wire to get even close.

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It would be best to know the exact used toroid, the number of turns used and the makeup of the wire to get even close.
I wrote this many times: Inductors are the hardest components to replicate. I even have listed ~20 different parameters somewhere on this forum...
   
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Ok, so there is resonance involved, is that needed?

I shortened the leads from C1 to R1 / D2 from 10 to 5cm and reduced the leads from my 21.8V PS (Vload) from 50 to 15cm.

There is some change, but only a little, see screenshot.

What components are involved for this inductance to get resonance?


After many experiments, it seems almost impossible to get the same traces, as all toroids and number of turns on them i used up till now all show a different outcome in trace shape.
It would be best to know the exact used toroid, the number of turns used and the makeup of the wire to get even close.

Itsu

Itsu,

Yes, I understand what you are saying and I also agree with Verpies.  However, at this point you could check the overall performance of your circuit in comparison to my post #519.  IOW, do you exhibit OU when calculating from your various measurements in a similar fashion as in my original post?

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yes, i could do that, but your COP calculations are not what i would expect, but doing it that way i get:

===========================================================================================
Following your measurements in post #519 in a quick way.

My Voltage on the MOSFET bridge is 48.48V and my coil L1 is 8 turns resulting in a V/t=6.6v (L1 measures 2.485mH)

Measuring in between the cursors!

My SP1 shows: Red math 33.26W over 223.6us thus UVload=33.26*223.6e-6=7.436mJ  (see below "itsu SP1" screenshot).

MY SP2 shows: Current through R2 is 219.2mA over 223.6us thus UR2= .2192^2*100*223.6e-6=1.074mJ   (see below "itsu SP2" screenshot).

My SP3 shows: 13.91W over 231.2us thus  Uin=13.91*231.2e-6=3.216mJ  (see below "itsu SP3" screenshot).

COP = (7436 + 1074)/3216 = 2.64

=========================================================================================

In this way i disregarded the both SG inputs and the 12V 4049 / driver chips input.

Itsu
« Last Edit: 2024-11-07, 20:37:10 by Itsu »
   
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yes, i could do that, but your COP calculations are not what i would expect, but doing it that way i get:

===========================================================================================
Following your measurements in post #519 in a quick way.

My Voltage on the MOSFET bridge is 48.48V and my coil L1 is 8 turns resulting in a V/t=6.6v (L1 measures 2.485mH)

Measuring in between the cursors!

My SP1 shows: Red math 33.26W over 223.6us thus UVload=33.26*223.6e-6=7.436mJ  (see below "itsu SP1" screenshot).

MY SP2 shows: Current through R2 is 219.2mA over 223.6us thus UR2= .2192^2*100*223.6e-6=1.074mJ   (see below "itsu SP2" screenshot).

My SP3 shows: 13.91W over 231.2us thus  Uin=13.91*231.2e-6=3.216mJ  (see below "itsu SP3" screenshot).

COP = (7436 + 1074)/3216 = 2.64

=========================================================================================

In this way i disregarded the both SG inputs and the 12V 4049 / driver chips input.

Itsu

IMO, the input energy for the SG inputs and the 4049 driver chips will be small in comparison to the primary 3.217mJ input!

Pm
   

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Correct, the 12.05V for the 4049 and drivers inputs 240mW over 317us, thus 0.24*317-6=78uJ

Itsu
   
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Correct, the 12.05V for the 4049 and drivers inputs 240mW over 317us, thus 0.24*317-6=78uJ

Itsu

Good Job!  O0

Pm
   

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its all your work  O0

How to continue now?     Improve on the COP of course, but how can we exploit this?

Can we change the Vload PS for a battery or super cap and pull the excess energy from that? 

Itsu

   
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its all your work  O0

How to continue now?     Improve on the COP of course, but how can we exploit this?

Can we change the Vload PS for a battery or super cap and pull the excess energy from that? 

Itsu

Itsu,

I'm working on charging a LAB efficiently but in the meantime, you could play with lowering the value of the load resistor R2 below 100 ohms.  Lower it until you have an average of nearly zero watts measured in Vload.  IOW, the average current feeding into Vload will be nearly zero amps and the power output will be generated only by the current in R2.  The take COP measurements to compare to your present number.

Regards,
Pm
   

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I reduced R2 to 7.5 Ohm to get near zero average power  / current, see SP1

My Voltage on the MOSFET bridge is 48.48V and my coil L1 is 8 turns resulting in a V/t=6.6v (L1 measures 2.485mH)

Measuring in between the cursors!

SP1 shows: Red math 1.425W over 223.6us thus UVload=1.425*223.6e-6=319uJ

SP2 shows: Current through R2 is 2.791A over 223.6us thus UR2= 2.791^2*7.5*223.6e-6=13.063mJ

SP3 shows: 14.62W over 231.2us thus  Uin=14.62*231.2e-6=3.385mJ

COP = (319 + 13063)/3385 = 3.95



EDIT,   the "near zero SP2" screenshot does not belong to the calculations made, as somehow i did not update the screenshot belonging to a later measurement.
        This shows that the circuit / measurements are rather sensitive and moving a (current) probe can cause already a different result as before.
        The positive is that the COP stays above 1 mostly all the time.



Itsu
« Last Edit: 2024-11-09, 09:39:36 by Itsu »
   
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its all your work  O0

How to continue now?     Improve on the COP of course, but how can we exploit this?

Can we change the Vload PS for a battery or super cap and pull the excess energy from that? 

Itsu

Wow!  great progress...
Congratulations, Jon and Itsu!

If I may suggest something - would much appreciate an effort to SIMPLIFY the circuit further where possible, so that replications are more straightforward. 

Getting the oscilloscope out of the requirement would be a great step forward, IMHO.

Can you start with a charged cap for input, output cap uncharged - then charge the output cap and simply compare Eout/Ein...?
   
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I reduced R2 to 7.5 Ohm to get near zero average power  / current, see SP1

My Voltage on the MOSFET bridge is 48.48V and my coil L1 is 8 turns resulting in a V/t=6.6v (L1 measures 2.485mH)

Measuring in between the cursors!

SP1 shows: Red math 1.425W over 223.6us thus UVload=1.425*223.6e-6=319uJ

SP2 shows: Current through R2 is 2.791A over 223.6us thus UR2= 2.791^2*7.5*223.6e-6=13.063mJ

SP3 shows: 14.62W over 231.2us thus  Uin=14.62*231.2e-6=3.385mJ

COP = (319 + 13063)/3385 = 3.95



EDIT,   the "near zero SP2" screenshot does not belong to the calculations made, as somehow i did not update the screenshot belonging to a later measurement.
        This shows that the circuit / measurements are rather sensitive and moving a (current) probe can cause already a different result as before.
        The positive is that the COP stays above 1 mostly all the time.



Itsu

Again, good work Itsu!!

Pm
   
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