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Author Topic: Graham Gunderson Energy conference High COP demonstration  (Read 157814 times)
Group: Experimentalist
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@partzman: Thanks for those plots and the explanation.

For me, the bottom line is that my input and output power estimations agree with your results quite closely.

For the input power from the main DC power supply  I(L1)*V(etap) you have 262.23 mW average, and I estimated 266 mW average "by eyeballing".
For the output power dissipated in the 50R load resistor V(outcap)2/50 you have 227.14 mW average (the "V2"units on the plot are wrong because you simply used a constant "50" instead of specifying that is a resistance in Ohms, which of course should have resulted in an answer in units of Watts instead of V2.) And I estimated 231 mW average by eyeballing. Not bad for the old Mark I eyeballs!

I'm guessing that the difference is taken up in power dissipation in the resistances of the coils and mosfets.


What happens to the reactive power result if you equalize the "on" duration of the gate voltage sources V7 and V3?

That is, for V7 use
PULSE(0 15 0 20ns 20ns 20us 30us)
and for V3 use
PULSE(0 15 10us 20ns 20ns 20us 30us)

TK,

You're welcome. Yes I keep forgetting about LtSpice recognizing ohms in the plot! I'll have to give it a try.

BTW, I'd say you have really good eyes! :o

I've attached a stabilized plot with your timing change suggestions and the resulting math calcs.  If you had an idea in mind that didn't manifest in this plot, let me know what you are thinking and I'll see if it can be made to work.

pm
   
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Here is my version of Graham's H-bridge which differs from Spokane1's in the fact that I've placed the choke outside the bridge circuitry. This arrangement requires that all bridge switches be turned on during the clamp phase but otherwise operates as a current fed parallel resonant inverter.  Note that this device is using 100v DC for Vcc or the power supply.

The first pix is the complete schematic with a busy plot.

The second pix is a power plot with the various plot maths displayed for analysis. The overall COP can be seen to be  2.35/2.86 = .82.

Taking V(Ecap2) first, I have measured the average reactive power of V(ecap2)*I(L1) and Id(M2)*V(ecap2) for comparison. At 1.506w and 1.534w respectively they are very close with the difference being in the mosfet losses.

With V(Ecap), I measured the average reactive power of V(ecap)*I(L1) and Id(M3)*V(ecap) again for comparison.  Here we see -1.262w and 1.278w respectively with the differences being other circuit losses. The polarity difference seen is due to the current direction in L1 as used by LtSpice to make the calculation. The true reactive power across L1 is +1.262 with voltage and current considerations applied.

The point of this is that during the part of the cycle that the V(Ecap2) end of L1 is a positive going half-sine wave, +1.506w average reactive power is produced across L1 from the non-dot end to the dot end.  During the part of the cycle when the V(Ecap) end of L1 is a going positive going half-sine wave, +1.262w average reactive power is across L1 from the dot end to the non-dot end. Therefore the differential power for a complete cycle using these figures is 1.506-1.262 = .244w reactive power.  The real to reactive power COP = 2.351/.244 = 9.63.

A similar comparison can be made using the measurements made with the M2 and M3 drain currents and the result will vary due to the additional small circuit losses but the real to reactive COP will still be >1.

pm     
   
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Gentlemen,

Folks disregard this attached drawing an go down to Post #435 and copy that one. This one is missing some components.

In my simulations of the H-Bridge circuit I have found that two of the MOSFETS are not active therefore making them unneeded. Upon further examination I have found that the entire H-Bridge can be replaced with one switch and a diode. The input to the primary of the Gunderson Transformer is the same in that it produces the same voltage and current wave forms with far fewer components.

k4zep made additional simplifications by proposing that the switching elements be placed on the low side of the circuit to better reference driver connections. This circuit variation also simulates the same as a full four element H-Bridge.

Graham said 7/18/2016 that he was planning to redo his H-Bridge with a two switch design. He also said that providing schematics to his demonstration device would be pointless since he was planning to re-do all the circuits. Both statements seem to be correct.

Anyway, here is the proposed simplified circuit. The elimination of three switching elements should reduce the gate leakage issue by 50%.

Does anyone see any issues with this design and why it might not work as good as a full H-Bridge in this application?

Oops the polarity on the 220 VDC power supply is backwards.

Spokane1
« Last Edit: 2016-08-18, 21:12:12 by Spokane 1 »
   
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Gentlemen,

Here is my take on the operation of the Synchronous Diode.

Comments Welcomed!

Spokane1
   
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@Spokane1: I see you have specified a 7808 regulator in your Logic Controller in the Simplified Schematic 02. But the absolute maximum Vcc values for the 74AC14 and the 74HC123 chips are only 7 volts, with 6 volts being the maximum recommended operating value.

So is this the "overdriving" mentioned in Gunderson's philosophy... or just a way to eat up more chips while experimenting?    :D


Also, it's hard for me to understand how a half-bridge or a single mosfet can produce the same results as a full, properly operating H-bridge. The full H-bridge should be capable of producing an "AC" voltage output with a peak-to-peak value of about twice the DC power supply value, shouldn't it? How can a single mosfet switch arrangement do this? Maybe you can explain this to me in terms I might be able to understand.    :-\
   
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TK,

You're welcome. Yes I keep forgetting about LtSpice recognizing ohms in the plot! I'll have to give it a try.

BTW, I'd say you have really good eyes! :o

I've attached a stabilized plot with your timing change suggestions and the resulting math calcs.  If you had an idea in mind that didn't manifest in this plot, let me know what you are thinking and I'll see if it can be made to work.

pm
It's hard for me to interpret what's going on since your plot contains a fairly long portion of constant values and these values are included in the "average" calculations listed below the plot.
I was thinking that by equalizing the driver pulse on-times and running the exact same calculations as before you might get a different but interesting result than you got before. (in reply #421)
   
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Gentlemen,

Here is my take on the operation of the Synchronous Diode.

Comments Welcomed!

Spokane1
Nice work... but unfortunately even magical SiC mosfets don't switch instantaneously like our thought-experiment SPST switches do. I've reproduced the Cree mosfet switching time parameters in the images attached below from the Data Sheet. As you can see, a 1 ns wide "harvest pulse" from the gate driver won't have any real effect at all and even a 100 ns pulse will likely be problematic.

Also, in your diagram your Gate trigger pulses in the top drawing seem to show long LOW intervals and short HIGH intervals.  But the other two drawings imply that the mosfets are ON (Gate signal HIGH) for 99+% of the time and are turned OFF (Gate signal LOW) for a very short pulse.  Am I misinterpreting something here?
   
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Posts: 1180
Gentlemen,

Here is my take on the operation of the Synchronous Diode.

Comments Welcomed!

Spokane1

Spokane1,

I have a little different opinion on the operation of the synchronous fets in the secondary.

If I understand your theory, energy is harvested or shuttled from the secondary into the load during the short "off" time of the fets, correct? IMO, your circuit would clamp the secondary field collapse voltage to approximately one diode drop above the output load voltage. Why would Graham have used such high voltage devices in this case?

OTOH, if the synchronous fets are on and conducting current from the secondary to the load for most of the cycle and then turned off for a short period, the secondary current and mmf rapidly reverses. During this time, the fet drains are subjected to a high voltage pulse which is generated by the collapse of the secondary current. The current reversal is created by the discharge of the energy stored in the fet's drain to gate and drain to source capacitances created by the peak voltage and current.  If the fet should avalanche at too low a voltage, the current reversal will be less than desired for proper operation. This action would then justify the high voltage fets used in G's circuit IMO.

Just my 2 pennies worth! :)

pm
   
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@partzman, Spokane1:

Can you please post the LTSpice .asc files you are using for your various sims? The only one I've got is partzman's GG3.asc.
   
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Posts: 79
@Spokane1: I see you have specified a 7808 regulator in your Logic Controller in the Simplified Schematic 02. But the absolute maximum Vcc values for the 74AC14 and the 74HC123 chips are only 7 volts, with 6 volts being the maximum recommended operating value.

So is this the "overdriving" mentioned in Gunderson's philosophy... or just a way to eat up more chips while experimenting?    :D


Also, it's hard for me to understand how a half-bridge or a single mosfet can produce the same results as a full, properly operating H-bridge. The full H-bridge should be capable of producing an "AC" voltage output with a peak-to-peak value of about twice the DC power supply value, shouldn't it? How can a single mosfet switch arrangement do this? Maybe you can explain this to me in terms I might be able to understand.    :-\

Dear TK,

That is easy enough. I screwed up (which has been happening a lot today).

I thought these were CMOS devices and performed better at higher voltages. I couldn't recall what that value was so I WAGed 8V. The ones I'm using at home are regular TTL and are running at 5V through a 7805 linear regular.

Spokane1
   
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Posts: 79
Dear All,

Speaking of screw up's I forgot to include the 1 uF discharge capacitor in the simplified schematic.

Here is a revision:

Spokane1
   
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Posts: 79
Nice work... but unfortunately even magical SiC mosfets don't switch instantaneously like our thought-experiment SPST switches do. I've reproduced the Cree mosfet switching time parameters in the images attached below from the Data Sheet. As you can see, a 1 ns wide "harvest pulse" from the gate driver won't have any real effect at all and even a 100 ns pulse will likely be problematic.

Also, in your diagram your Gate trigger pulses in the top drawing seem to show long LOW intervals and short HIGH intervals.  But the other two drawings imply that the mosfets are ON (Gate signal HIGH) for 99+% of the time and are turned OFF (Gate signal LOW) for a very short pulse.  Am I misinterpreting something here?

Dear TK,

Your are correct in that real world switches can't respond that fast and to be accurate should be shown with sloping lines to account for the transition times.

The intent of my chart is to show the gross timing sequence of various events taking place in the primary circuit - as I seem them at the moment. Had I had this chart 4 weeks ago it would have helped me. Perhaps it might help others.

It is a work in progress and any presentation suggestions are appreciated.

As far as the illustrated gate triggers go I may well have the polarity reversed inconsistently from diagram to diagram. I can hardly see which is which with that black background LC Spices uses.  The intent is to show where the harvest pulse takes place and how short it is compared to the oscillation period. The intent is to have the MOSFETS on most of the time and off for just a brief moment. Which ever polarity achieves this is the one I intended.

Spokane1
   
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@partzman, Spokane1:

Can you please post the LTSpice .asc files you are using for your various sims? The only one I've got is partzman's GG3.asc.

TK,

Here are the .asc files for the sims I've posted.

pm
   
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Posts: 79
@partzman, Spokane1:

Can you please post the LTSpice .asc files you are using for your various sims? The only one I've got is partzman's GG3.asc.

Dear TK,

Sure thing as soon as this work computer gets fixed and I can read a thumb drive.

Spokane1
   
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Posts: 79
Spokane1,

I have a little different opinion on the operation of the synchronous fets in the secondary.

pm

Dear partzman,

Well Great, that is how we have half a chance at getting to the bottom of this interesting phenomena.


Spokane1,

If I understand your theory, energy is harvested or shuttled from the secondary into the load during the short "off" time of the fets, correct? IMO, your circuit would clamp the secondary field collapse voltage to approximately one diode drop above the output load voltage. Why would Graham have used such high voltage devices in this case?
pm


I'm not so sure we will observe a complete classical field collapse in this topology. True the current has been blocked for one coil, but the other coil is still moving the same amount of current is was before. I believe that in order to have a full and fast field collapse all the current must be removed. Here we still have magnetic flux generated from the primary still sloshing around and the continued current from 1/2 the secondary.  I'm sure something is going to happen. According to Grahams calculated magnetic flux diagram we get a saw tooth waveform. I don't know just how much voltage is generated from the demonstrated flux change - and it is beyond me to calculate it.


Spokane1,

OTOH, if the synchronous fets are on and conducting current from the secondary to the load for most of the cycle and then turned off for a short period, the secondary current and mmf rapidly reverses. During this time, the fet drains are subjected to a high voltage pulse which is generated by the collapse of the secondary current. The current reversal is created by the discharge of the energy stored in the fet's drain to gate and drain to source capacitances created by the peak voltage and current.  If the fet should avalanche at too low a voltage, the current reversal will be less than desired for proper operation. This action would then justify the high voltage fets used in G's circuit IMO.


My transformer theory skills have always been weak. I failed EE431 that dealt with motors and transformers (However I did get an "A' in the lab portion). We shall have to take this discussion up again once I have working apparatus to take measurement from. I am getting closer on that front. I wonder if anyone else is?

Spokane1
   
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@partzman: Thanks!

@Spokane1: You can change the color of the waveform plot background and just about everything else in the Tools>Color Preferences menu item.
   
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Posts: 79
Dear All,

While we are talking theory today here is my take on what is going on in the Primary circuit.

Spokane1
   
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Posts: 79
@partzman: Thanks!

@Spokane1: You can change the color of the waveform plot background and just about everything else in the Tools>Color Preferences menu item.

Thanks, I shall check that out. I thought there had to be some method to change the background.

Spokane1
   

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Believing in something false doesn't make it true.
The talk about shorting coils and so forth reminded me of this video I did a a couple of months ago.  Here is a repost of that post with video and schematic.  Any comments are welcome.

 Hi Graham,

I finally got around to testing your idea you got from Erfinder.  I modified the circuit a little for test purposes.  I used my Picaxe microprocessor for my pulsing circuit instead of the 555 timer circuit.  This let me control more precisely the timing and width of the pulses.  I also added a bridge rectifier across the secondary to help with the analysis of the circuit.  I have attached the revised circuit and a video of the results.  Kind of interesting.  Not sure if there is anything useful in this or not but still interesting, at least to me.

https://youtu.be/g5jdL3BSH28

Anyone on this forum is welcome to look at the video and discuss it.  But please do not share this video with anyone not on this forum.  It is not listed on YouTube.  It is not posted for public discussion or comment.

Take care,
Carroll
------------------------


---------------------------
Just because it is on YouTube does not make it real.
   
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@Spokane1: I've taken the liberty of rearranging your Simplified Schematic 03 a little bit to fit my understanding of the physical arrangement. Would you please check it over and see if I've gotten the basic ideas correct? Thanks in advance....

   
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Posts: 79
@Spokane1: I've taken the liberty of rearranging your Simplified Schematic 03 a little bit to fit my understanding of the physical arrangement. Would you please check it over and see if I've gotten the basic ideas correct? Thanks in advance....

Dear TK,

Take all the liberty you want with anything I post here. This is a joint effort to determine if Graham accidently did stumble onto something good.

Your Revised drawing looks great. I shall revise my CAD drawing to match. The functional layout is easier to read with your approach.

By the way, how did you edit that drawing so quickly?

Spokane1
   
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Posts: 79
Also, it's hard for me to understand how a half-bridge or a single mosfet can produce the same results as a full, properly operating H-bridge. The full H-bridge should be capable of producing an "AC" voltage output with a peak-to-peak value of about twice the DC power supply value, shouldn't it? How can a single mosfet switch arrangement do this? Maybe you can explain this to me in terms I might be able to understand.    :-\

Dear TK,

I don't know if it will really will work this way, this is just the simulation telling me that it will produce the same input wave function to the parallel tank. I hope it works that way, this will reduce greatly the cost of replication.

Attached is a jpg of the circuit. I shall get you the support files tomorrow.

Spokane1
   

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OTOH, if the synchronous fets are on and conducting current from the secondary to the load for most of the cycle and then turned off for a short period, the secondary current and mmf rapidly reverses.
I agree. That reversal happens during one half of high frequency LC oscillation and is vividly described by GG in his MIT video around the time index 1h05m (with water in an aquarium analogy)

During this time, the fet drains are subjected to a high voltage pulse which is generated by the collapse of the secondary current.
I agree

The current reversal is created by the discharge of the energy stored in the fet's drain to gate and drain to source capacitances created by the peak voltage and current. 
Not only in capacitance but also in the inductance of the transformer.
Capacitances do not react to an open circuit with high voltage - inductances do.

If the fet should avalanche at too low a voltage, the current reversal will be less than desired for proper operation. This action would then justify the high voltage fets used in G's circuit IMO.
I agree


P.S.
Did you ever try to model 4 isolated DC voltage sources being switched by ideal switches into the gates of these MOSFETs forming the "synchronous diode"  and calculating how much current from these 4 sources gets to the "output terminals" of this "synchronous diode" ?
« Last Edit: 2016-08-19, 16:30:15 by verpies »
   
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Dear TK,

Here are the support files for the circuit shown in post #446.

Spokane1
   
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I agree. That reversal happens during one half of high frequency LC oscillation and is vividly described by GG in his MIT video around the time index 1h05m (with water in an aquarium analogy)
I agree
Not only in capacitance but also in the inductance of the transformer.
Capacitances do not react to an open circuit with high voltage - inductances do.

Yes, as I re-read my sentence, I realize how poor my description was! I agree and what I should have included is that the fet's capacitance dumps it's energy back into the secondary inductance to complete the current reversal.
Quote
I agree


P.S.
Did you ever try to model 4 isolated DC voltage sources being switched by ideal switches into the gates of these MOSFETs forming the "synchronous diode"  and calculating how much current from these 4 sources gets to the "output terminals" of this "synchronous diode" ?

No I haven't up to this point. I guess I could measure the currents in my sims using the IRF831s but they will be conservative in comparison to the Cree devices IMO. I have Cree's models of their mosfets but since I'm not sure exactly how Graham's output circuit is configured, I haven't used them in any sims to date. Spokane's two secondary output has one secondary capable of a high voltage collapse while the other secondary is limited by the substrate diode clamp to the load voltage!?! Maybe this is the actual design and perhaps that is why Graham commented on his surprise that the secondary worked forcing him to re-check his connections!

pm
   
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