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Author Topic: Graham Gunderson Energy conference High COP demonstration  (Read 213002 times)
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Dear Spokan1

Thanks for the extra insight and all your hard work on this project. If you have not already offered the photos you took at his home will you be doing that, or are those photos confidential?


Dear ION,

The photos are available to anybody who has use for them. Its just that they are to big at 2 MB+ per photo to place here. I have 40 of them. I can only send about 6 at a time to most people's mail box.  I have posted them here in the 800 pixel resolution when a particular subject under discussion comes up.  I'm sure anyone who is actually attempting to build a replication circuit could benefit from looking at them.

Rieyuki set up a Google drop box, but I couldn't get it to work due to the lack of a password.

Send me your email  using the forum message service and I shall be happy to send them to you (6 at a time)

Spokane1
   
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Dear Spokane1

Attached are two methods to generate a negative supply. Each has merits and drawbacks. Just roughed in (not optimized) and tested in LTSpice.

Regulators not shown for simplicity, but utilize the raw outputs. You should pick the one that best seems to match the photos.

Graham could have eliminated a lot of extra complexity by closing the loop and dispensing with the regulators, but I guess he had his reasons.

Dear ION,

Hey that looks great, especially this first one. It seems to match the dual diode component layout we see on the circuit board.  It looks like I shall be redrafting that drawing next week.

As far as his reasons go I believe that voltage isolation was a big design consideration. In my Spice simulations I'm seeing some very high voltages develop in the tank circuit. I'm sure that Graham saw the same thing develop in his simulations, so he designed this high voltage separation approach, or so I think.

Also I'm not so sure all those little epoxy transistor looking things are regulators, that was just a WAG that seem to fit for the first schematic draft. If they were transistors I would expect more support components.

Spokane1
   
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If they are 78Lxx series regulators (79L05 for the negative 5V) in TO-92 packages, they have a peak current rating of 100 - 140 mA depending on manufacturer.  Is this (78L12) enough to turn on a SiC mosfet through a gate driver at 50 - 75 kHz?
   
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Dear ION,

The photos are available to anybody who has use for them. Its just that they are to big at 2 MB+ per photo to place here. I have 40 of them. I can only send about 6 at a time to most people's mail box.  I have posted them here in the 800 pixel resolution when a particular subject under discussion comes up.  I'm sure anyone who is actually attempting to build a replication circuit could benefit from looking at them.

Rieyuki set up a Google drop box, but I couldn't get it to work due to the lack of a password.

Send me your email  using the forum message service and I shall be happy to send them to you (6 at a time)

Spokane1

Dear Spokane1

Thanks for your kind offer, but you've got enough on your plate right now.

I think Chet or Slider remembers how to get to the ftp site that was setup here, maybe we can make a folder for the information repository of this device and include the photos there in one big upload (when you have more time).

Regards, ION


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Buy me some coffee
ION

The ftp site we had setup was on the previous server and no longer exists, i dont have a problem with him uploading them here, each post has a size limit on this forum so the way to do it is to upload 1 and then keep modifying the post gradually adding them 1 by 1.

Regards
Peter
   
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I will assume this task if Spokane1 approves , perhaps in a separate thread in his bench section so he can moderate input delete , adjust and advise
as necessary.

As ION mentions, Spokane1 has quite a full plate already .

respectfully
Chet K
   

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Everyman decries immorality
One reason why I say a simple $20 Kill-A-Watt meter on his mains input could have helped to convince (or not) depending on the total input power reading.

Spokane1 only has three tasks that are worth pursuing and are relevant at this time:

1)  Replicate the device as accurately as he can.

2)  Integrate a $20 Kill-A-Watt meter into the circuit input.

3)  Analyse the results.


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From GG's demonstration of a sawtooth flux waveform I have taken the primary current waveform then deduced the secondary current needed to create that sawtooth, assuming normal transformer action where the flux comes from the difference between pri and sec ampere turns.  Done crudely from my sketched waveforms.  And I get a secondary current very much like that shown by GG.  So I deduce that there is no significant flux leakage and my original estimate of the primary flux waveshape is wrong.

Smudge   
   
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Spokane1 only has three tasks that are worth pursuing and are relevant at this time:

1)  Replicate the device as accurately as he can.

2)  Integrate a $20 Kill-A-Watt meter into the circuit input.

3)  Analyse the results.

All,

This could amount to 3-6 months work or maybe a lifetime!  I'm assuming most want to see if this is "OU".  So, take a large multi farad cap. bank and let the output charge it.  Run a simple high efficient inverter off that bank to power the front end via a isolation transformer, close the loop.  See what happens to the voltage on the Cap. Assuming there is some feedback to prevent running away in the circuits, the voltage on the cap should remain constant, and it should run on and on and on and on.  Even better, then add a small load to the output to show it is actually doing "Work".     ;D  I know of at least 3 people that will be working this in some form or another.  Myself, I'm more into research as to "why" it works and to understand the transformer part of the device. Building by rote simply does not work without understanding been there, done that. Time will tell!

Ben K4ZEP



   
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From GG's demonstration of a sawtooth flux waveform I have taken the primary current waveform then deduced the secondary current needed to create that sawtooth, assuming normal transformer action where the flux comes from the difference between pri and sec ampere turns.  Done crudely from my sketched waveforms.  And I get a secondary current very much like that shown by GG.  So I deduce that there is no significant flux leakage and my original estimate of the primary flux waveshape is wrong.

Smudge

What is your rationale for the statement "no significant flux leakage" considering the 10 mil mylar spacer between the "U" sections and the large physical distance between primary and secondary coils? What approximate level would be considered significant?

On another note, I am happy to try to simulate any simple drive circuit that we suspect could produce even some very small continuous DC on the secondary, without the use of rectifiers. We know from classical induction theory (and practice), this is supposedly not possible.

Ben said:
Quote
Myself, I'm more into research as to "why" it works and to understand the transformer part of the device. Building by rote simply does not work without understanding been there, done that.

Smudge has offered his thoughts on a possible mechanism, and I agree, we become another "cargo cult" if we only copy without understanding.
http://www.sjsu.edu/faculty/watkins/cargocult.htm

Working up a hypothesis with bench experiments seems a very worthy route. In GG's entire conference, he never hinted at the idea he had in the back of his mind to build such a device in the first place. He does say the discovery was accidental.

Regards. ION


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GG shows the secondary waveform that he integrates (or rather the 'scope integrates) to get the flux.  This is not DC although there is almost a continuous negative DC plateau.  But that intermittent plateau has enormous positive spikes.  So the transformer does not produce DC.  Only after rectification is there a DC output.

As regards leakage I originally integrated the input voltage to get primary flux and that suggested considerable flux leakage because thaat waveshape could not produce the secondary voltage.  Now that the difference between pri and sec current creates the sawtooth flux we have normal transformer action in that regard.  So IMO the input voltage waveform shown by GG is not taken across the primary, but earlier in the circuit, perhaps ahead of some capacitance or inductance.  Of course there will be a small leakage flux but I can't determine its magnitude.

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Here is a different topological approach to Graham's device that utilizes a current fed parallel resonant inverter with a clamp phase and a pulsed rectifier. The uniqueness IMO is the common mode power consumption at Etap and differential power across the primaries L2 and L4 between Ecap and Ecap2. The transformer is linear in this example.

The first pix shows the busy plot with schematic. Some .meas calcs are shown that give the DC input power, the output power, plus the resulting COP.

The second pix shows one full cycle and the resulting plot maths for the cycle. The "if" statements are reasonably synchronized to V(Ecap) and V(Ecap2) respectively to be able to see the power of each branch. The power in at Etap is equaled by the sum of the power in each branch as can be seen while at the same time, the total power across the primary network branches of L2 and L4 is a net of ~-8mw.

Therefore it my conclusion that this circuit simulates OU in reference to the reactive power across the primaries compared to the resistive load output power.

Fire away! 8)

pm
   
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PM, very nice!!

I like the idea of the current fed center tap p-p approach over the H bridge, it eliminates all the messy high side drive requirements, and is easier to test on the bench.

I'll study it further, but I'm a novice at LTSpice.

Regards
ION

P.S. I don't see the timing for pulse generators V1, V3 and V7, I guess they were cut off the schematic.

Also, new to me is the stacking  of the power supply sources V2, V8. plus I can't scroll the Spice error log to see the calculations because it is a screen capture.

If you are inclined, please post the .asc file so I can study it more deeply. Thanks much!


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Input scope probe positions. The big Red and Black clips are the leads to the Tek P5205 High-Voltage Differential Voltage Probe. I still don't know the part number of the Current Probe.
   
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PM, very nice!!

I like the idea of the current fed center tap p-p approach over the H bridge, it eliminates all the messy high side drive requirements, and is easier to test on the bench.

I'll study it further, but I'm a novice at LTSpice.

Regards
ION

P.S. I don't see the timing for pulse generators V1, V3 and V7, I guess they were cut off the schematic.

Also, new to me is the stacking  of the power supply sources V2, V8. plus I can't scroll the Spice error log to see the calculations because it is a screen capture.

If you are inclined, please post the .asc file so I can study it more deeply. Thanks much!

ION,

Thanks.

I didn't include the generator signals to save from more confusion on the plots. I can show a plot with these but I've attached the asc file below so you can play with the device.

Sorry about V2 as it really is not needed. It is simply a lossless current sensor made with a zero voltage source but the current thru L1 is identical so V2 is redundant.

I did crop the error log so it would fit on the capture but you should be able to see the Iin, Pin, Eout, Pout, and COP numbers.

pm

Edit: The asc file attached just fine like Poynt said so I don't know what in the world I was trying to attach previously! 
   
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Thanks pm.  :)


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When analyzing the input circuit branches of the GG3, there appear to be some interesting details IMO over the time period shown in the plot that is attached.

The beginning current of L1 is 14.289ma and ends at 12.139ma for a loss of 2.15ma. This equates to an energy loss in L1 of 2.84uJ or 148mW over the 19.2us period. Note that during this same time period,  the average power output is 232mW.

What creates this loss of current in L1?  Observe the average voltage at Etap of 31.182v during this time period which is in opposition to the 20v DC of Vcc. Therefore due to di = E*dt/L, Etap forces a reverse current of (31.182-20)*19.2e-6/.1 = 2.15ma which is equal to the lost current in L1 during this period.

The currents in L2 and L4 are also interesting.  The current in L2 starts at 73.746ma and ends the period at 97.77ma with L4 following at ~14ma less.

Do these observations offer any potential for OU?

pm

   
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From GG's demonstration of a sawtooth flux waveform I have taken the primary current waveform then deduced the secondary current needed to create that sawtooth, assuming normal transformer action where the flux comes from the difference between pri and sec ampere turns.  Done crudely from my sketched waveforms.  And I get a secondary current very much like that shown by GG.  So I deduce that there is no significant flux leakage and my original estimate of the primary flux waveshape is wrong.

Smudge

Dear Smudge,

You seem to have a handle on the magnetic situation going on in the secondary. I was wondering if you would like to take a stab at what I have noticed in my simulations.

The operation of the primary tank circuit seems to follow what Graham showed in his presentation. The big difference is what is not happening in the secondary after the synchronous diode gets  a harvest command pulse.

In the simulation, using an ideal transformer with a K of .8588 (or so) and no provisions for saturation, much less the different split core parameters, there is hardly any impact on the secondary current except a hardly noticeable blip.

In Graham's presentation the operation of the synchronous diode on the secondary current is profound.

Any idea's as to what might be happening here and how the simulation can be changes to better match Graham's version?

Spokane1
   
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from pm:
Quote
When analyzing the input circuit branches of the GG3, there appear to be some interesting details IMO over the time period shown in the plot that is attached.

The beginning current of L1 is 14.289ma and ends at 12.139ma for a loss of 2.15ma. This equates to an energy loss in L1 of 2.84uJ or 148mW over the 19.2us period. Note that during this same time period,  the average power output is 232mW.

What creates this loss of current in L1?  Observe the average voltage at Etap of 31.182v during this time period which is in opposition to the 20v DC of Vcc. Therefore due to di = E*dt/L, Etap forces a reverse current of (31.182-20)*19.2e-6/.1 = 2.15ma which is equal to the lost current in L1 during this period.

The currents in L2 and L4 are also interesting.  The current in L2 starts at 73.746ma and ends the period at 97.77ma with L4 following at ~14ma less.

Do these observations offer any potential for OU?

pm

Interesting observations, pm.

I was wondering what could be done to improve the efficiency of the circuit such as changing all DC resistance in the inductors to zero ohms and maybe replacing the FET's with pure switches or alternately modify the "Rds on" to zero ohms in the model.

Substituting pure switches might also eliminate gate injection, which may not be a major factor in this sim.

Do you have any ideas for optimization?

Unfortunately, I lack the skill to properly analyze and comment on the sim, and need to get further up the learning curve.

Keep the good work coming  O0

Regards, ION


---------------------------
"Secrecy, secret societies and secret groups have always been repugnant to a free and open society"......John F Kennedy
   
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Input scope probe positions. The big Red and Black clips are the leads to the Tek P5205 High-Voltage Differential Voltage Probe. I still don't know the part number of the Current Probe.

Dear TK

I don't have the model number of that current probe, but if I ever get it I shall forward it to you.

About all we have to go on is that it cost $1,500 in 2000, is a Hall chip device,  and was purchased about the same time the Tek scope was.

Do you have any idea what could have been purchased back then for that kind of money? There can't be more than five or so manufactures that made that kind of stuff back then and they all probably offered the same kind of product.

Maybe this is the kind of device where vast differences between the manufacturer's offerings existed, and maybe still do.  Maybe each model has important configuration differences based upon current range and design of sensing amplifiers.

I know this is not much help for this kind of question.

Spokane1
   
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Dear All,

I have secured some 3C90 ferrite cores from Surplus Sales of Nebraska. So far no luck finding the high permittivity versions of the same size.

Spokane1
   
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from pm:
Interesting observations, pm.

I was wondering what could be done to improve the efficiency of the circuit such as changing all DC resistance in the inductors to zero ohms and maybe replacing the FET's with pure switches or alternately modify the "Rds on" to zero ohms in the model.

Substituting pure switches might also eliminate gate injection, which may not be a major factor in this sim.

Do you have any ideas for optimization?

Unfortunately, I lack the skill to properly analyze and comment on the sim, and need to get further up the learning curve.

Keep the good work coming  O0

Regards, ION

ION,

Thanks for reading!

I used the IRF831s because I have then on hand for bench tests if needed and really wanted somewhat realistic losses in the sim.

You will find that if you try to use zero ohms for inductors, switches, etc, LtSpice will not start. If it does, it will not converge. So, one must have a small amount of resistance in the inductors and switches and yes the efficiency could be improved by reducing the values I used. However, disregarding the gate drive losses, the drain to source losses for M1 and M2 are 440uW and 394uW during each half cycle on time and 37mW and 6.5mW during the clamp time. I haven't calculated the losses for M3 at the moment.

Regarding other optimization, apart from your suggestions I really don't have any more to offer atm.

I do not presently understand how energy can be taken from the primary circuit branches to deplete the energy in L1 during the first 19.us of the cycle and see the energies increase in L2 and L4 while at the same time producing power in the load! ???

pm

 
   
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Dear TK

I don't have the model number of that current probe, but if I ever get it I shall forward it to you.

About all we have to go on is that it cost $1,500 in 2000, is a Hall chip device,  and was purchased about the same time the Tek scope was.

Do you have any idea what could have been purchased back then for that kind of money? There can't be more than five or so manufactures that made that kind of stuff back then and they all probably offered the same kind of product.

Maybe this is the kind of device where vast differences between the manufacturer's offerings existed, and maybe still do.  Maybe each model has important configuration differences based upon current range and design of sensing amplifiers.

I know this is not much help for this kind of question.

Spokane1

Yes, indeed there are vast differences in current probes and indeed they all have their particular configuration differences, quirks and foibles. Bandwidth, DC offset and propagation delay characteristics are very important. Good ones cost a pretty penny today and always have done. Frankly, I get depressed and feeling faint whenever I look at current probes. The LeCroy AC-DC current probe I used in this demonstration cost over 3,000 dollars when it was new.

http://www.youtube.com/watch?v=KWDfrzBIxoQ

It is far simpler and generally more precise to use a properly-arranged Current Viewing Resistor and monitor the Vdrop across that item with ordinary passive probe(s) or a specially constructed Kelvin probe arrangement. If signal isolation is a problem during simultaneous measurements of V and I,  there are various ways around that.

As to Gunderson's Tektronix probe -- that's about all I can tell from the photos, that it is a Tek probe, of mid-recent manufacture. Maybe someone else can do the digging necessary to identify it. Here are the photos of the probe that I have found:
   
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It's not as complicated as it may seem...
I still don't know the part number of the Current Probe.
It may be either a TCP0030 (DC-120MHz) or a TCP202 (DC-50MHz) (a common choice).

Perhaps even a P6021 (120Hz-60MHz).
   
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